Versal™ ACAP (Adaptive Compute Acceleration Platform) is a highly integrated, multi-core compute platform that can adapt to evolving and diverse algorithms. The VCK190 is one of first released Xilinx Versal AI Core evaluation devices.

This blog entry walks you through the design creation steps below:

1. Building a Versal based IP Integrator design in Vivado
2. Creating the device image
3. Building platform and system projects in Vitis
4. Running and debugging the applications on the VCK190 evaluation board
   

PS-GEM on Versal 

The Gigabit Ethernet MAC (GEM) provides a hard 10/100/1000 Mbps interface per IEEE 802.3-2016.

There are two GEM controllers in the PS Low-power Domain (LPD).

Each controller is operated independently and includes a management data input/output (MDIO) interface for its external PHY, for use with the RGMII interface.

 GEM is made up of the following components:

• A MAC controlling transmit, receive, address checking, and loopback
• Configuration registers providing control and status registers, statistics registers, and synchronization logic
• A Direct Memory Access controlling DMA transmit and DMA receive
• A Timestamp Unit (TSU) to calculate the IEEE 1588 timer values which contains the real time clock

In system applications where no DMA operation is required, the DMA module can be removed using a configuration option and an external FIFO interface can be used to incorporate GEM into a SoC environment.

The GEM block includes the following signal interfaces:

• GMII and RGMII to an external PHY
• An MDIO interface for external PHY management
• An APB slave interface for accessing the GEM’s registers
• An AXI4 DMA master interface for memory access
• An optional FIFO interface in applications where DMA functionality is not required
• An optional timestamp interface

The I/O options include the following:

• RGMII (v2.0) routed to the LPD MIO pins for connection to an external PHY
• GMII and MII routed to the PL where they can be mapped to GTs or optionally can be converted to other protocols using the PL logic
• Diagnostic internal loopback within each controller

Note: an internal SERDES interface (SGMII) is not supported in Versal. It is supported in MPSoC devices.

On VCK190 devices, GEM0 and GEM1 are hard-wired to two external RGMII PHYs on the board.

There are two RJ45 ports which are for GEM0 and GEM1 respectively. If testing the GEM1 RGMII port, please make sure that the GEM0 RGMII port is also connected with a cable as they use the shared MDIO line which uses GEM0 MDIO as a master.  

Please see below a screenshot of the VCK190. On the top right, there are two RJ45 ports for Versal Ethernet.

Creating an IP Integrator design in Vivado

Please download the attached Tcl file and follow the steps below.

1. Create a project in Vivado 2019.2 based on a VCK190 board.
2. Create a Block Design.
3. Source vck190_1g.tcl. Here is the block diagram in the IP Integrator Canvas. 
4. Generate the HDL wrapper file.
5. Click on “Run Implementation” and “Generate Device Image”. 
6. Export the hardware design with the device image included.

Note: Some connections between CIPs and the NoC are missing when “run block automation” is used on its own. The attached Tcl file can be used to ensure correct configuration settings in CIPs and the NoC.

Building and Running the LwIP Application in Vitis

We have already built the IP Integrator design and exported the hardware design with the device image. Now we are going to create the lwIP example application in Vitis and run it on the VCK190 board.

1. Launch Vitis.
2. Create the Application Project with the XSA file from the above design.
3. Select the “lwIP Echo Server” example from SDK.
4. Build the Platform and System projects in SDK.
   When the lwIP echo server application is selected, the BSP settings for the lwIP library are set automatically.
   Users can also choose to create and build the platform project only, but BSP settings will then need to be set manually. 
5. Run the lwIP example on the VCK190 board.
   Below is the output of the UART console:
6. Here is the output of the ping test:

In order to change to GEM1 RJ45 for testing, users should modify the platform_config.h with XPAR_XEMACPS_1_BASEADDR.

Ethernet defines can be found in xparameters.h in the BSP.

Please see the example below:

In platform_config.h, change the following define:

Update this define to the following:

#define PLATFORM_EMAC_BASEADDR XPAR_XEMACPS_1_BASEADDR

You can now rebuild the application and run the test again.

LwIP performance

Below are the BSP settings of the lwIP echo server application.

• PARAMETER dhcp_does_arp_check = true
• PARAMETER lwip_dhcp = true
• PARAMETER pbuf_pool_size = 2048

With lwIP TCP/UDP perf applications, the below parameters are set by default.

• PARAMETER mem_size = 524288
• PARAMETER memp_n_pbuf = 1024
• PARAMETER n_tx_descriptors = 512
• PARAMETER pbuf_pool_size = 16384

The lwIP parameters are important for tuning performance.

Users should refer to the sections “Configuring Memory Options”, “Configuring Packet Buffer (Pbuf) Memory Options” and “TEMAC Adapter Options” in the lwIP library documentation to see more information on each parameter:

https://www.xilinx.com/support/documentation/user_guides/ug1137-zynq-ultrascale-mpsoc-swdev.pdf

These parameters control how much memory and how many Pbufs and descriptors are allocated and used.

If the system is strapped and unable to process the packets, the BDs and Pbufs will be used up quickly and will not be freed as quickly as is required. Performance will suffer as a result.

However, we should also balance how much memory can be used, so these parameters are tuned to optimal values for 1Gbps on the evaluation boards we use for performance benchmarking. This can be used as a reference for you to tune the parameters for your own requirements.

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Source: https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Bringing-Up-a-1G-Ethernet-Interface-on-a-Versal-device/ba-p/1092703