Synopsys’ Steve Pateras explains the basics of silicon lifecycle management and how it can help monitor, analyze, and optimize both semiconductor and end-user systems throughout the product value chain, from design and manufacturing to testing and maintenance.

Siemens’ Heather George considers the current state of 3D chiplet-based designs and efforts to standardize chiplet models and deliverables as well as system and package workflows to facilitate chiplet ecosystems.

Cadence’s Vinod Khera considers how the metaverse can help to accelerate the innovation time and reduce the cost of semiconductor design by creating a hybrid virtual environment in which development and testing are done as a combined human-machine enterprise.

Riscure’s Ramiro Pareja points to the latest attack on a car’s remote keyless entry system, and find the  same keyfob vulnerabilities repeated over and over again, including weak cryptography, insecure key management, and unprotected hardware and software.

Ansys’ Milan Redon checks out how engineers improve the sound quality of products by analyzing a variety of sound metrics, including the measure of frequency components in the overall sound, or tonality.

SEMI’s Margaret Kindling and Berton Mahardja highlight workforce development issues, including increasing industry image and awareness, hiring veterans and a diversity of people, and introduce a career exploration platform.

Memory analyst Jim Handy considers reports of chips made by U.S. companies being found in Russian missiles used to attack Ukraine, and ways that could have happened.

Plus, check out the blogs featured in last week’s Low Power-High Performance newsletter:

Rambus’ Emma-Jane Crozier explains why displays in next-generation cars are set to get even bigger and more sophisticated.

Arm’s Remy Pottier predicts the metaverse will touch every aspect of technology development, from personal devices to cloud networks.

Synopsys’ Soni Kapoor points out the advantages of seeing the effects of layout while it’s still in progress.

Ansys’ Erik Ferguson and University of Arizona’s Daewook Kim highlight the structural and optical simulation requirements of next-generation telescope optics.

Cadence’s Frank Schirrmeister explains why the energy impact of electronics has multiple layers and must be considered holistically.

Synopsys’ Anand Thiruvengadam looks at eliminating four key bottlenecks in memory development, in Memory Design Shift Left To Achieve Faster Development Turnaround Time.

KLA’s Richard Barnett explains how to separate individual die in a wafer using chemical methods.

Siemens EDA’s Nebabie Kebebew and Nigel Bleasdale lay out why on-premises compute capacity has become a bottleneck for circuit simulation.