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Tag: System-Level Design

WEBINAR: Why Rigorous Testing is So Important for PCI Express 6.0 – Semiwiki

In the age of rapid technological innovation, hyperscale datacenters are evolving at a breakneck pace. With the continued advancements in CPUs, GPUs, accelerators, and...

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TSMC 2023 North America Technology Symposium Overview Part 5

TSMC also covered manufacturing excellence. The TSMC “Trusted Foundry” tagline has many aspects to it but manufacturing is a critical one. TSMC is the...

True 3D Is Much Tougher Than 2.5D

Creating real 3D designs is proving to be much more complex and difficult than 2.5D, requiring significant innovation in both technology and tools. While there...

Startup Funding: January 2023

Quantum computing had a good month in January, collectively raising over $240 million. A significant chunk of that went to a full-stack quantum company...

Boosting Data Center Memory Performance In The Zettabyte Era With HBM3

We are living in the Zettabyte era, a term first coined by Cisco. Most of the world’s data has been created over the...

Blog Review: Nov. 2

Systems & Design ...

A Power-First Approach

It is becoming evidently clear that heat will be the limiter for the future of semiconductors. Already, large percentages of a chip are dark...

Bespoke Silicon Rattles Chip Design Ecosystem

Bespoke silicon developers are shaking up relationships, priorities, and methodologies across the semiconductor industry, creating demand for skills that cross traditional boundaries, and driving...

EDA, IP Revenue Way Up

Systems & Design ...

Cybord: Electronic Component Traceability

Counterfeit electronics is a multibillion-dollar industry worldwide. The challenge is finding them, and this is where Israeli startup Cybord is working to gain a...

Extending The Benefits Of UVM To Include AMS: An Update On Accellera’s UVM-AMS Standard Development

By Tom Fitzpatrick and Peter Grove SoC teams can be divided up into design and verification groups. For digital designs, the Universal Verification Methodology (UVM),...

Verification Methodologies Evolve, But Slowly

Semiconductor Engineering sat down to discuss digital twins and what is required to develop and verify new chips across a variety of industries, such...

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