Many of the Video IP cores come with example designs. These designs are used to showcase the IP, as well as to provide an example that can be used for reference when using the IP core in your own design.
These IP Example designs are usually described in Chapter 5 of the IP’s product guide.
Product guides can be found on the IPs product page, in Document Navigator, or in the Video Design Hub.
HDMI VCU118 Example Design Overview
There are two Xilinx HDMI IP cores, a Source IP core (HDMI 1.4/2.0 TX Subsystem) and a Sink IP core (HDMI 1.4/2.0 RX Subsystem).
These IP cores are described in (PG235) and (PG236). Chapter 5 of these Product Guides contains a table listing the HDMI 1.4/2.0 example designs.
As the table shows, there is a VCU118 example design, but no VCU128 example design.
Note: As the table lists, there is no DRU clock available in passthrough mode because there is no oscillator pinned out to a gtrefclk in the banks near the HDMI core.
Tutorial
Here are the steps I used to port the HDMI VCU118 design to the VCU128 board. These steps are meant to be used as an example, and this is not the only way that it can be done.
1. The first step when porting a design is to make sure that the new hardware platform is built so that it can support the design.
The best way to begin is to list the requirements for the HDMI design. By using Figure 5-3 from the Product Guide, and focusing on the I/O (highlighted) we can see what the design requires.
Note: the VCU118 board does not have the nidru gtrefclk and neither does the VCU128.
List of requirements:
- TMDS clock pinned out to FMC
- 3 GT pins for TX data pinned out to FMC
- TX reference clock pinned in from FMC
- RX reference clock pinned out to FMC
- RX reference clock pinned in from FMC
- 3 GT pins for RX data pinned out to FMC
- **Double-check surrounding banks for programmable NI-DRU clock source
2. Now that we know the requirements, we can check the VCU128 to make sure that they exist.
To do this, we can check the VCU128 schematic, VCU128 board user guide, and wiki pinout.xml against the FMC document (diagram shown below).
Using the documents above, we can translate the list into pin names.
M2C -> Mezzanine to Carrier (FMC->Board)
C2M -> Carrier to Mezzanine (Board->FMC)
- TMDS clock pinned out to FMC -> LA27_P
- 3 GT pins for TX data pinned out to FMC -> DP0_C2M_P through DP2_C2M_P
- TX reference clock pinned in from FMC -> GBTCLK1_M2C_P
- RX reference clock pinned out to FMC -> LA00_CC_P
- RX reference clock pinned in from FMC -> GBTCLK0_M2C_P
- 3 GT pins for RX data pinned out to FMC -> DP0_M2C_P through DP2_M2C_P
- **Double-check surrounding banks for programmable NI-DRU clock source
- No clocks near bank124 that can be used
Looking at the design, we can see that there are more pins which are not shown in Figure 5-3.
- Si5324 RST
- FMC_IIC_SCL
- FMC_IIC_SDA
- rs232_uart_rxd ->UART0_RXD
- rs232_uart_txd ->UART0_TXD
- reset -> CPU_Reset
- RX_DDC_OUT_scl_io ->LA16_P
- RX_DDC_OUT_sda_io ->LA16_N
- TX_DDC_OUT_scl_io->29_P
- TX_DDC_OUT_sda_io->29_N
- TX_EN_OUT ->LA26_P
- TX_CLK_SEL_FPGA -> LA18_CC_P
- Used to select whether the 4th GT or the LVDS pins are used as the HDMI TMDS clock.
- RX_HPD_OUT -> LA20_N
- RX_I2C_EN_N_OUT -> LA22_P
- RX_DET_IN -> LA03_P
- SI5324_LOL_IN ->LA02_N
- TX_HPD_IN -> LA31_N
3. Now that we know that the I/O pins exist and are connected to the FMC properly, let’s build the VCU118 example design.
Note: this process is described in Chapter 5 of the Product Guides.
4. Once the design has been built, we need to update any specific VCU118 parameters. This will keep connections from being removed when we change the part number.
In this design, the only IP targeted directly at the VCU118 is the MMCM.
4.1. Open the mb_ss_0 block and open the clock wizard (clk_wiz).
4.2. Clear board parameters. This will remove the VCU specific parameters.
4.3. Update the source to be differential and save the block design.
5. Set the project to a new target -> VCU128 (XCVU37P-L2FSVH2892E)
6. Update the IP to the new project
Open IP Integrator, select report IP status, then upgrade all IP.
Verify that there are no errors.
Note: This is not guaranteed to work for all designs or ports. If this step does not work, use the previous design as an example and build a new project by hand.
7. Now that the project is targeting the VCU128 and the IP is upgraded, we need to edit the VPHY to target the correct bank and use the correct clocks.
From the VCU128 documents, we know that the GTs used are in bank 124. Bank 124, is X0Y0.
Because the GTs are in banks 124, but we are using the TX reference0 clock from bank 125, we need to set the reference clock to southrefclk0.
8. Because we are using a North/South refclk, we need to update the pinout as described in (PG230) the Vivado PHY Controller Product Guide.
8. Double-check your connections and make sure that all pins are connected, then verify the design and run synthesis.
9. Once Synthesis is complete, we can update the constraints.
Open the synthesized design, then select layout -> I/O planning.
In this view, select I/O ports and then update them with the new pinout. (GT TX/RX pins will already be populated)
Once you are done, save so that the constraints file (.xdc) is updated.
10. Now that the constraints are updated, run implementation and generate a bitstream.
11. Export hardware for SDK.
Select File -> Export Hardware
11. Finally, build the application example design using the same flow for the VCU118.
Open SDK
Create a new BSP (File -> New SDK)
Use the MSS tab to select the HDMI 1.4/2.0 RX Subsystem driver and click on Import Examples.
In the tab that opens, select Passthrough MicroBlaze.
This will generate the software project. Build this and the ELF will now be created.
12. Done! Test in hardware to verify that the ported example design is working.
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Source: https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Video-Blog-How-to-port-the-HDMI-example-design-for-a-VCU118/ba-p/1027650
