We are currently experiencing a pivotal moment concerning the automotive industry. Three major technology areas are converging. First, there is an enormous demand for advanced driver-assistance systems (ADAS) coupled with the increasing trend toward autonomy. Second is the digitization and electrification of everything, which is driving the need for efficient compute. Third is the trend to highly advanced digital cockpits and in-vehicle infotainment (IVI) systems to provide the best user experience.

To address these technology areas, many companies are creating sophisticated system-on-chip (SoC) devices featuring multiple heterogeneous central processing unit (CPU) cores. These SoCs often include one or more graphics processing unit (GPU) cores and—more recently—a neural processing unit (NPU) core, which can perform artificial intelligence (AI) and machine learning (ML) tasks much faster than traditional processors while consuming a fraction of the power.

Arm processor IP and Arteris system IP

Even outside of the automotive design community, it is widely known that Arm processor IP is ubiquitous in the automotive industry. What may be less known is that Arteris system IP is used in over 70% of today’s ADAS SoCs already, and the complexity of other automotive domains beyond ADAS drives the need for network-on-chip (NoC) automation in similar ways.

In particular, Arteris FlexNoC interconnect IP is used by the world’s top automotive semiconductor design teams as the backbone for their on-chip communications. Irrespective of whether the design employs AMBA AXI3, AXI4, AHB, APB, OCP, PIF or a proprietary protocol, Arteris FlexNoC reduces the number of wires by nearly one-half, resulting in fewer gates and a more compact chip floor plan.

Fig. 1: Automotive electronics innovation with Arm processor IP and Arteris system IP.

One of the biggest problems with multi-core processing systems is maintaining cache coherence. This is not easy, even in homogeneous systems where all processor cores are the same type. Maintaining cache coherence in heterogeneous systems is much more difficult because processing elements may differ in their coherent interface protocols, cache state models, cache line sizes, caching structure sizing and associativity, transaction race conditions and other features. To address this issue, the world’s top automotive semiconductor design teams employ Arteris Ncore cache coherent interconnect IP, which is the industry’s only multi-protocol AMBA CHI and ACE cache coherent interconnect. In addition to being optimized for heterogeneous cache coherent systems, Ncore is highly scalable through a typical 50% reduction in pin count, thus reducing area and power while leading to an efficient layout.

Addressing the automotive paradigm shift

Arm and Arteris have been collaborating for many years. To provide just a few examples, in June 2011, it was announced that Arteris was supporting the deployment of Arm’s AMBA 4 ACE specification. In April 2013, it was announced that Arm and Arteris were extending the partnership to deliver additional interconnect options to SoC designers. On May 2016, Arteris Ncore cache coherent interconnect IP was enabled by Arm’s cycle-accurate models. And in November 2018, the companies gave a joint presentation, “Implementing ISO 26262 Compliant AI Systems with Arm and Arteris IP.” This presentation described how AI and ML acceleration IP from Arm (like the Arm NPU and Mali C71) could be implemented in ISO 26262-compliant automotive systems with the help of functional safety mechanisms in the Arteris FlexNoC and Ncore interconnects.

Now, in order to address the current automotive paradigm shift, Arm and Arteris have extended their partnership to deliver automotive solutions using Arm AE processors and Arteris interconnect IP. These solutions will provide advanced safety and security capabilities to the automotive market, with Arm having licensed a portfolio of released and future Arm Cortex CPUs to Arteris to expand and accelerate the delivery of such solutions.

Fig. 2: The new collaboration between Arm and Arteris will provide seamless integration, well-aligned roadmaps and optimized flows for QoR and safety.

What does this mean to designers? Well, as just one example, when Arm announces a new processor core, its leading ecosystem partners are ready to hit the ground running because, behind the scenes, they have been collaborating on the new design to ensure compatibility.

This new partnership with Arm puts Arteris on the same level, which means the two companies can fully align their roadmaps to deliver seamless integration that results in optimized flows for the best quality of results (QoR) and safety, all of which is key to delivering customer success.