This Blog covers how to use the AXI Interrupt Controller (INTC) in cases where you need to route more that 16 interrupts to the PS from IP cores in the PL. We are using Xilinx peripherals including GPIOs in the Vivado design. 

The example design is created in the 2020.2 version of Vivado, targeting a VCK190 evaluation board. Interrupts are tested on PetaLinux 2020.2, and the design Tcl and system-user.dtsi file are attached.

AXI GPIO:

The General Purpose Input/output (GPIO) core is an interface that provides easy access to the internal properties of the device. This core can also be used to control the behavior of the external devices.

Interrupts:

The Interrupts control gets the interrupt status from the GPIO channels and generates an interrupt to the host. It is enabled when the Enable Interrupt option is set in Vivado.

For input mode, gpio_input pins are connected to the PUSH BUTTONS of the VCK190 as follows:

° gpio_input(0) = GPIO_SW15

° gpio_input(1) = GPIO_SW14

° gpio_input(2) = GPIO_SW16

° gpio_input(3) = GPIO_SW17

° gpio_input(3) = GPIO_SW18

AXI INTC:

The AXI Interrupt Controller (INTC) core concentrates multiple interrupt inputs from peripheral devices to a single interrupt output to the system processor.

The registers are used for checking, enabling, and acknowledging interrupts.

The main purpose of this example is to connect more that 16 interrupts to the PS. The AXI INTC core allows us to fulfill this requirement. We can go up to 32 interrupts if using one AXI INTC block, and you can make use of cascading. (We might cover an example of this in another blog entry).

In the next couple of diagrams where we discuss the Concat IP, you can see how the interrupts are connected.

Block Design:

I have not added a diagram of the complete design all at once as it’s too large, so the required connections are shown separately below.

Concat IP:

The Concat IP core provides a mechanism to combine bus signals of varying widths into a single bus.

Add the Concat block from the IP catalog, and double-click the IP to open the Re-customize IP dialog box. 

Set the “Number of Posts” parameter to the number of input ports desired. In this example 18 are selected.

This is how it looks after customizing the IP; the 18th port is connected to the GPIO_PUSH_BUTTONS interrupt line as discussed previously.

dout is the output port whose bit width equals the combined bit widths of all of the input ports which is routed to the input intr port of the AXI INTC core.

The output of the AXI INTC is connected to the pl_ps_irq_0 port of the Versal CIPS block:

Validate the design and follow the remaining steps to generating the bitstream.

Export the hardware for building the PetaLinux images.

PetaLinux:

Kernel Configuration:

The following options are enabled in the configuration. They are normally enabled by default but you should check just in case.

• Device Drivers
  • GPIO Support
    • Memory Mapped GPIO Drivers
      • Xilinx GPIO support
      • Xilinx Zynq GPIO support
  • Input device support
    • Keyboards
      • GPIO Buttons
      • Polled GPIO buttons

Adding Push Buttons to the Device tree:

Push Buttons are available only for the Input GPIO application.

Each created sub-node controls a single bit of GPIO. Under the “gpio-keys” keys node in the dts file, create sub-nodes for Push Buttons as per the design with names shown below:

Once this is done, boot Linux. You can see the labels of Push Buttons SW15 to SW18 in cat /proc/interrupts. 

When you press the Push Buttons randomly, the trigger count increases as shown below:

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Source: https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/How-to-handle-more-that-16-interrupts-on-a-Versal-device/ba-p/1223286