Optimized chiplet arrangement; verification; FeFET crossbar array; circuit activity fingerprinting; HW trojan threats to chiplets; compiler augmentation; new HW accelerator; connecting quantum with sound; electronic/photonic chip sandwich; Sparseloop in HW accelerator design flows.
New technical papers added to Semiconductor Engineering’s library this week.
If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involved for us posting links to papers. Please send suggestions (via comments section below) for what else you’d like us to incorporate.
Related Reading
Technical Paper Library home
Chip Industry’s Technical Paper Roundup: Nov. 29
Carbon nanotube transistors; XDA Of flip-chip packaged FinFET devices; analog low-dropout voltage regulators; variations in silicon photonic circuits; EV charging cybersecurity; how 2D materials expand; vdW material properties; nanoscale 3D printing; 3D structuring inside GaAs by ULI.
Linda Christensen
(all posts)
Linda Christensen is vice president of operations and a contributing writer at Semiconductor Engineering.
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- Source: https://semiengineering.com/chip-industrys-technical-paper-roundup-dec-5/
