Compute-in-memory; HW generators; distributed training on Frontier for LLMs; GaN and SiC Power Devices; in-memory computing for neuromorphic systems; FeFET CAM cells for storage-class memory; chemical accuracy with shallow quantum circuits; HW Trojans in shared cloud FPGAs.
New technical papers added to Semiconductor Engineering’s library this week.
| Technical Paper | Research Organizations |
|---|---|
| WWW: What, When, Where to Compute-in-Memory | Purdue University |
| Correct and Compositional Hardware Generators | Cornell University |
| Optimizing Distributed Training on Frontier for Large Language Models | ORNL and Universite Paris-Saclay |
| Review and Outlook on GaN and SiC Power Devices: Industrial State-of-the-Art, Applications, and Perspectives | University of Padova |
| Mosaic: in-memory computing and routing for small-world spike-based neuromorphic systems | CEA-LETI Université Grenoble Alpes, University of Zurich, and ETH Zurich |
| Ferroelectric Field Effect Transistors–Based Content-Addressable Storage-Class Memory | IPMS and IIT Madras |
| Towards chemical accuracy with shallow quantum circuits: A Clifford-based Hamiltonian engineering approach | Caltech, Microsoft Research AI4Science Lab, and Tencent Quantum Lab |
| X-Attack 2.0: The Risk of Power Wasters and Satisfiability Don’t-Care Hardware Trojans to Shared Cloud FPGAs | EPFL, Cyber-Defence Campus, and Northwestern Polytechnical University |
More Reading
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- Source: https://semiengineering.com/chip-industry-technical-paper-roundup-jan-23/
