Breker Verification Systems will demonstrate its new RISC-V CoreAssurance™ and SoCReady™ SystemVIP™ along with its Trek Test Suite Synthesis portfolio during the 61st Design Automation Conference (DAC) in Booth #2447. DAC will be held from Monday, June 24, through Wednesday, June 26, from 10 a.m. until 6 p.m. at Moscone West in San Francisco.
RISC-V cores require an extensive amount of verification, including capabilities uncommon in general block verification, required to achieve the quality bar set by Arm and X86. RISC-V processor core verification can be considered as a stack of verification tests starting with basic operational tests, ISA compatibility and micro-architectural testing, then leading to integrity and integration testing to ensure system level compatibility, and performance testing.
Breker’s RISC-V CoreAssurance SystemVIP provides the complete range of tests for the entire RISC-V core verification stack. Starting with randomized instruction generation and microarchitectural scenarios, SystemVIP includes tests that check all integrity levels ensuring the smooth application of the core into an SoC, regardless of architecture, and the evaluation of possible performance and power bottlenecks and functional issues.
It can be extended for custom RISC-V instructions to be incorporated into the complete test suite crossed with other tests. It is self-checking and incorporates debug and coverage analysis solutions and can be ported across simulation, emulation, prototyping, post-silicon and virtual platform environments.
The Breker SoCReady SystemVIP extends these capabilities for teams integrating RISC-V processors on SoCs needing to ensure SoC issues such as load store efficiency, interrupt testing, coherency, security and more are fully evaluated. It is also useful to ensure the quality of RISC-V cores obtained from other vendors.
Based on synthesis technology, the SystemVIP amplifies scenario models to improve coverage and bug hunting. An AI technique called Planning Algorithms explores the state space of the various scenarios starting with the desired end space and working backward to initial inputs. This technique allows for precise test execution that tracks from input to specific states leading to more effective bug hunting with fewer tests than a more general hit and miss randomized approach.
Test cross combination is another synthesis technique that combines various scenario components in a multi-dimensional series of tests. For example, crossing different privilege levels with branch prediction and load store scenarios to build combined tests grows the odds of an unusual corner case issue occurring.
Scheduling concurrent scenarios further increases pressure on design components to reveal difficult bottlenecks in design architecture by “torturing” the device to reveal weaknesses. Tests are scheduled together across HARTS and multicore processors that overload SoC resources, allowing the performance of the tests to be examined in a profiling window.
Breker’s SystemVIPs are used for a variety of complex RISC-V core designs, including system coherency in a multicore SoC. integrity test sets, high-coverage core test, power domain switching, hardware security access rules and automated packet generation
Breker’s RISC-V CoreAssurance and SoCReady SystemVIPs are available now as are its Test Suite Synthesis solutions. Pricing is available upon request. For more information, visit the Breker website or email info@brekersystems.com. To arrange a demonstration or private meeting at DAC, send email to info@brekersystems.com.
DAC registration is open.
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