In this blog I will share the steps for running a Hello world on the industry first 7nm Versal ACAP devices. You will also learn about the similarities and differences between the Zynq® UltraScale+™ MPSoC, and Versal™ ACAP design flow.
In this entry I will first run through the Zynq MPSoC flow, followed by the Versal ACAP flow.
Zynq MPSoC |
Hardware Overview |
Zynq UltraScale+ MPSoC is the Xilinx second-generation Zynq platform, combining a powerful processing system (PS) and user-programmable logic (PL) into the same device. The processing system features the Arm® flagship Cortex®-A53 64-bit quad-core or the dual-core processor and Cortex-R5F dual-core real-time processor. |
System Block Diagram |
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Available Evaluation Boards |
Tools Support |
Vivado, Vitis™ |
Documentation |
1.Embedded Design Tutorial Link: https://github.com/Xilinx/Embedded-Design-Tutorials/tree/master/docs/Introduction/ZynqMPSoC-EDT 2.MPSoc Example Designs: https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/444006775/Zynq+UltraScale+MPSoC 3. Technical Reference Manual https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf |
Video Walk-through Tutorials |
Processing System Block |
Zynq MPSoC Block |
Project Wizard Settings |
Create Block Design |
System Properties Settings |
Processing System IP |
Step1: Click on the add IP or ‘+‘ button Step2: Search Zynq MpSoC Step3: Click OK to add the IP. |
IP Block Diagram |
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Block Automation |
You will now use a preset template created for the ZCU102 board. Click the Run Block Automation Link. This configuration wizard enables many peripherals in the Processing System with some multiplexed I/O (MIO) pins assigned to them according to the board layout of the ZCU102 board. For example, UART0 and UART1 are enabled. The UART signals are connected to a USB-UART connector through UART to the USB converter chip on the |
Validate Design |
Right-click in the white space of the Block Diagram view and select Validate Design. Alternatively, you can press the F6 key. Note: A message dialog box will open and states “Validation successful. There are no errors or critical warnings in this design.” |
Generate Output Products |
1. In the Block Design view, click the Sources tab. 2. Select Let Vivado Manage Wrapper and auto-update and click OK. 3. Click Generate. |
Generate Device Image |
Go to Flow Navigator→ Program and Debug and click Generate Device Bitstream. (.bit)
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Export Hardware |
To write a hardware platform using the GUI, follow these steps: 1. Select File → Export → Export Hardware in the Vivado Design Suite. The Export Hardware Platform window opens. 6.Click Finish to generate the hardware platform file in the specified path.
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Build Software for PS Subsystems |
1. Launch the Vitis IDE from the Windows start menu shortcut or by double-clicking the C:XilinxVitis2020.1binvitis.bat file. 2. Select the workspace and continue.
3. Select File → New → Application Project. 4. 4. Select Create from hardware specification (XSA). Browse the XSA file and provide the platform name. Click Next.
5. Provide the Application project name and select the Processor. Click Next. Processor: psu_cortexa53_0 6. Select the Operating system and Architecture. Operating System: Standalone Architecture: 64-bit 7. Click Next.
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Application Template |
Select the Hello World template. Click Finish.
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Build Project |
Now build the hardware by right-clicking Platform → Build Project.
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Run Configuration |
1. Right-click on the system project edt_zcu102 and select Run As → Run Configurations. The Run Configuration dialog box opens. 2. Double-click System Project Debug to create a Run Configuration. 3. Set the HW target as needed. 4. Click Run.
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Versal ACAP |
Hardware Overview |
The Versal ACAP includes several processors, each with different computation capabilities to meet application needs. All devices, including the processing system (PS), the platform management controller (PMC), and the network on chip (NoC) interconnect to enable all processors to reach the DDR memory controllers and other resources within the device. All Versal devices include programmable logic (PL). The Processing System includes an Arm Cortex-A72 dual-core processor along with the system memory management unit (SMMU) and the cache coherent interface (CCI) unit and Arm Cortex-R5F dual-core processor for applications requiring safety and deterministic execution times. |
System Block Diagram |
Available Evaluation Boards |
Tools Support |
Vivado, Vitis |
Documentation |
1. Embedded Design Tutorial Link: https://github.com/Xilinx/Embedded-Design-Tutorials/tree/2020.2/Versal-EDT 2. Versal Example Designs: https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/487489537/Versal+Example+Designs 3. Technical Reference Manual https://www.xilinx.com/support/documentation/architecture-manuals/am011-versal-acap-trm.pdf |
Video Walk-through Tutorials |
Processing System Block |
Versal ACAP Control, Interface and Processing IP (CIPS) |
Project Wizard Settings |
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Create Block Design |
System Properties Settings |
Processing System IP |
Step1: Click on the add IP or ‘+‘ button Step2: Search for CIPS Step3: Click OK to add the IP. |
IP Block Diagram |
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Block Automation |
By default, the CIPS does not have any control or interfaces enabled. Applying the board preset enables those peripherals on the CIPS that have board connections to their MIO pins. Double-click on CIPS IP, choose cips fixed io from the board tab as shown in the following figure & click OK.
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Validate Design |
Right-click in the white space of the Block Diagram view and select Validate Design. Alternatively, you can press the F6 key. Note: A message dialog box opens and states “Validation successful. There are no errors or critical warnings in this design.” |
Generate Output Products |
1. In the Block Design view, click the Sources tab. 2. Select Let Vivado Manage Wrapper and auto-update and click OK. 3. Click Generate. |
Generate Device Image |
Go to Flow Navigator→ Program and Debug and click Generate Device Image.(.pdi)
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Export Hardware |
To write a hardware platform using the GUI, follow these steps: 1. Select File → Export → Export Hardware in the Vivado Design Suite. The Export Hardware Platform window opens. 6. Click Finish to generate the hardware platform file in the specified path. |
Build Software for PS Subsystems |
1.Launch the Vitis IDE from the Windows start menu shortcut or by double-clicking the C:XilinxVitis2020.1binvitis.bat file. 2.Select the workspace and continue.
3. Select File → New → Application Project. 4. Select Create from hardware specification (XSA). Browse to the XSA file and provide the platform name. Click Next.
5. Provide the Application project name and select the Processor. Click Next. Processor: psv_cortexa72_0 6. Select the Operating system and Architecture. Operating System: Standalone Architecture: 64-bit 7. Click Next.
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Application Template |
Select the Hello World template. Click Finish.
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Build Project |
Now build the hardware by right-clicking Platform → Build Project.
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Run Configuration |
1. Right-click on the system project design_1_wrapper and select Run As → Run Configurations. The Run Configuration dialog box opens. 2. Double-click System Project Debug to create a Run Configuration. 3. Set the HW target as needed. 4. Click Run
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Source: https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Vivado-Vitis-2020-2-Zynq-MPSoC-Hello-World-to-Versal-ACAP-Hello/ba-p/1201294