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Tag: academic papers

University students recruit AI to write essays for them. Now what?

Feature As word of students using AI to automatically complete essays continues to spread, some lecturers are beginning to rethink how they should teach...

Food startups Aleph Farms and Iron Ox grow from net zero roots

Cultivating a net zero emissions goal is core to the business models and missions of food startups Aleph Farms and Iron Ox. As each...

ECB Blog Post Insists This Is ‘Bitcoin’s Last Stand,’ Officials Claim BTC Is Headed Toward ‘Irrelevance’

On Wednesday, Nov. 30, 2022, a blog post published by the European Central Bank (ECB) discusses bitcoin and the authors Ulrich Bindseil and Jürgen...

The Generative AI Revolution in Games

To understand how radically gaming is about to be transformed by Generative AI, look no further than this recent Twitter post by @emmanuel_2m. In this post he explores using Stable Diffusion + Dreambooth, popular 2D Generative AI models, to …

The post The Generative AI Revolution in Games appeared first on Andreessen Horowitz.

The resurrection of tellurium as an elemental two-dimensional semiconductor

Purdue University researchers review the recent progress in synthesizing atomically thin Te two-dimensional (2D) films and one-dimensional (1D) nanowires, including applications in field-effect transistors & potential for building ultra-scaled CMOS circuits.

The post The resurrection of tellurium as an elemental two-dimensional semiconductor appeared first on Semiconductor Engineering.

Flat-surface-assisted and self-regulated oxidation resistance of Cu(111)

Researchers develop copper thin films that are semi-permanently oxidation resistant because they consist of flat surfaces with only occasional mono-atomic steps.

The post Flat-surface-assisted and self-regulated oxidation resistance of Cu(111) appeared first on Semiconductor Engineering.

An Energy-Efficient DRAM Cache Architecture for Mobile Platforms With PCM-Based Main Memory

Researchers propose "CAMP", a novel DRAM cache architecture for mobile platforms having PCM-based main memory.

The post An Energy-Efficient DRAM Cache Architecture for Mobile Platforms With PCM-Based Main Memory appeared first on Semiconductor Engineering.

E/E Architecture Synthesis: Challenges and Technologies

ACADEMIC PAPER Abstract “In recent years, the electrical and/or electronic architecture of vehicles has been significantly evolving. The new generation of cars demands a considerable amount of computational power due to a large number of safety-critical applications and driver-assisted functionalities. Consequently, a high-performance computing unit is required to provide the demanded power and process these... » read more

The post E/E Architecture Synthesis: Challenges and Technologies appeared first on Semiconductor Engineering.

Key Recovery for Content Protection Using Ternary PUFs Designed with Pre-Formed ReRAM

Researchers from Northern Arizona University examine how ReRAM based solutions perform against SRAM PUF-based schemes in terms of BERs and tamper resistance. Funded by U.S. Air Force Research Laboratory (AFRL).

The post Key Recovery for Content Protection Using Ternary PUFs Designed with Pre-Formed ReRAM appeared first on Semiconductor Engineering.

A compact two elements MIMO antenna for 5G communication

Simple, miniaturized, and low-profile multiple-input multiple-output (MIMO) antenna operating at 29 GHz with reduced mutual coupling between the antenna elements for futuristic 5G communication.

The post A compact two elements MIMO antenna for 5G communication appeared first on Semiconductor Engineering.

2D materials for future heterogeneous electronics

Potential of 2D Materials for future scaling, More Than Moore, Photonic Integrated Circuits, Neuromorphic Computing and Quantum Computing.

The post 2D materials for future heterogeneous electronics appeared first on Semiconductor Engineering.

Vertical MoS2 transistors with sub-1-nm gate lengths

Side-wall MoS2 transistors with an atomically thin channel and a physical gate length of sub-1 nm using the edge of a graphene layer as the gate electrode

The post Vertical MoS<sub>2</sub> transistors with sub-1-nm gate lengths appeared first on Semiconductor Engineering.

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