The integrated block for PCIe Rev. 4.0 with DMA and CCIX Rev. 1.0 (CPM4) consists of two PCIe controllers, DMA features, CCIX features, and Network on Chip (NoC) integration.

The Versal™ ACAP CPM Mode for PCI Express enables direct access to the two high-performance, independently customizable PCIe controllers. The CPM4 uses up to 16 Versal device GTY channels over the XPIPE.

Application designs can also interface to the CPM4 with soft logic and clocking resources in the programmable logic. Because CPM4 is an integrated block, the user cannot probe the internal signals with Vivado ILA for debugging purpose.

The CPM4 block records various statuses and its configurations in registers. These registers are documented in (AM012).

This blog will illustrate how to read these registers and provides suggestions on which registers to read for debugging purpose.

The CPM4 register read and write can be done using the XSDB (Xilinx System Debugger). The below screen capture shows how to invoke the XSDB and connect to a Versal device.

AM012 provides different sets of registers depending on whether you are using PCIE Controller 0 or PCIE Controller 1. Select the appropriate link below to read the correct registers for debug.

https://www.xilinx.com/html_docs/registers/am012/am012-versal-register-reference.html#mod___cpm4_dma_attr.html
https://www.xilinx.com/html_docs/registers/am012/am012-versal-register-reference.html#mod___cpm4_pcie0_attr.html
https://www.xilinx.com/html_docs/registers/am012/am012-versal-register-reference.html#mod___cpm4_pcie1_attr.html
https://www.xilinx.com/html_docs/registers/am012/am012-versal-register-reference.html#mod___cpm4_xdma_csr.html

To check whether the phy_rdy is asserted or not, read the following register:

https://www.xilinx.com/html_docs/registers/am012/cpm4_pcie0_attr___phy_rdy.html#

When there is a potential link issue, always confirm whether phy_rdy is asserted.

GT Reset FSM Register

The register below provides the status of the GT reset FSM:

• 0xF72121D8
• 0xF72125D8
• 0xF72129D8
• 0xF7212DD8

• When the upper 24 bits are non-zero and the lower 8 bits are 0s, it indicates that the GT is out of reset.
• If there is a reset issue, the lower 8 bits might still show up as 0 but the upper 24 bits will also be 0s indicating that the GT is not yet out of reset.

Each register corresponds to the corresponding GT channel of a PCIe lane for a PCIe link.

LTSSM Register

The registers below provides LTSSM and other PCIe related statuses in PCIe use mode.

• 0xF721200C
• 0xF721240C
• 0xF721280C
• 0xF7212C0C

Bits [12:7] corresponds to the LTSSM state. For LTSSM encoding values, see (PG343).

Miscellaneous Registers

The following registers can also be helpful for debug:

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Source: https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Register-based-debugging-of-Versal-ACAP-CPM-Mode-for-PCI-Express/ba-p/1221922