The number of challenges is growing in power semiconductors, just as it is in traditional chips. Thermal dissipation and gradients, new design rules, and layout issues need to be considered, especially in the context of higher voltage and increased performance demands. Roland Jancke, design methodology head in Fraunhofer IIS’ Engineering of Adaptive Systems Division, talks about issues in integrating power semiconductors with other devices, different packaging impacts, and how these devices will degrade over time.

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