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Kyoto’s new KP-H photodiode achieves 40GHz bandwidth

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29 June 2020

Japan’s Kyoto Semiconductor Co Ltd has developed the KP-H KPDEH12L-CC1C lens-integrated chip-on-carrier indium gallium arsenide (InGaAs) high-speed photodiode to support 400Gbps transmission systems that use PAM4 (Pulse Amplitude Modulation 4) both within and between data centers.

Currently, Kyoto has achieved transmission speeds of mainly 100Gbps by bundling 4 lanes of 25Gbps. However, there are growing demands in the market for 400-800Gbps transmission speeds. The Institute of Electrical and Electronics Engineers (IEEE) set the PAM4 standard, which corresponds with 4-bit signal to one modulation. The transmission speed per photodiode reaches 50Gps (= 400Gps/4 lanes/2 (PAM4)). The transmission bandwidth required for the photodiode to achieve this speed is 35-40GHz.

With the introduction of the new photodiode, Kyoto is supporting the increasing speeds and capacity requirements for transmission systems in 5G networks and beyond.

Picture: Mounting of the KPDEH12L-CC1C photodiode (with integrated condenser lens) on the carrier.

The 0.6mm x 0.48mm x 0.25mm size of the carrier on which the photodiode is mounted, and the width and length of the electrode pattern formed on the surface of the board (with little attenuation at high frequencies), are optimized using electromagnetic simulation. As a result, Kyoto claims that it has achieved an industry-leading 400Gbps and 40GHz as a frequency band with an integrated transimpedance amplifier. The KP-H photodiode has passed Telcordia GR-468-Core qualification (the standard reliability test for communication equipment).

As well as being mounted on a carrier that is optimally designed to achieve high frequency, a condenser lens is integrated on the backside of the KPDEH12L-CC1C photodiode, allowing incoming light to collect in the light absorption area, and making it easy to align the optical fiber with the photodiode. The photodiode chip is mounted on a carrier twice as big as the chip itself.

Mass production of the KP-H KPDEH12L-CC1C photodiode is scheduled to start in November.

Tags: PIN photodiode

Visit: www.kyosemi.co.jp/en

Source: http://www.semiconductor-today.com/news_items/2020/jun/kyoto-290620.shtml

Semiconductor

DuPont Adds Boric Acid-Free Electrolytic Nickel to its Nikal™ BP…

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“Our plating chemistries have amassed a track record of superior performance and reliability through our continual focus on quality and innovation” said Dennis Chen, Global Business Director, Advanced Packaging Technologies, DuPont Electronics & Industrial

DuPont (NYSE: DD) Electronics & Industrial business (“DuPont”) announced it has expanded its family of Nikal™ BP plating chemistries with the addition of Nikal™ BP BAF Ni electrolytic nickel. The new chemistry is boric acid-free, making it an enhanced safety plating option for under-bump metallization (UBM) packaging applications.

UBM is an advanced packaging process that involves creating a thin-film metal layer stack between the integrated circuit (IC) or copper pillars and the solder bumps in a flip chip package. Critical to package reliability, the stack’s three key purposes are to:

  • Form the electrical connection between the die and the bump
  • Serve as a barrier to eliminate unwanted diffusion; and
  • Create the mechanical connection between the bump and bump pad.

With a focus on sustainability, DuPont integrates safer by design and green chemistry principles into its innovation processes, hence enabling a culture of learning and collaboration to develop sustainable solutions for the future. Nikal BP BAF Ni electrolytic nickel eliminates boric acid which is commonly used as a buffering agent in conventional nickel sulfamate baths for the UBM process. The new chemistry, using an alternative buffering agent, advances DuPont’s commitment to sustainability and accelerates the adoption of safer alternatives in the marketplace.

Nikal BP BAF Ni electrolytic nickel is characterized by its ability to produce low-porosity nickel deposits for wafer plating, making it particularly well suited for semiconductor wafer applications requiring low-stress nickel, solderable finishers, UBM barrier layers and bump plating. It also produces a superior basis layer for over-plating with gold, palladium, tin and tin-alloy processes on semiconductor components.

“Our plating chemistries have amassed a track record of superior performance and reliability through our continual focus on quality and innovation,” said Dennis Chen, Global Business Director, Advanced Packaging Technologies, DuPont Electronics & Industrial. “At the same time, we are committed to developing technology that incorporates sustainable concepts. We have integrated all of these aspects into this addition to our Nikal BP family.”

A single, ready-to-use chemistry, Nikal BP BAF Ni is low foaming with long bath life and yields smooth surface morphology, as well as excellent thickness uniformity. It offers ease of process control with inline metrology, and its compatibility with conventional Nikal BP Ni enables simple drop-in replacement for existing users.

Formulated to meet customers’ wide range of needs, DuPont’s proven Nikal BP chemistries deliver uniform deposits, excellent barrier capabilities, solderability, and other characteristics essential to consistent wafer fabrication.

Interested customers should contact their account managers to learn more about the Nikal BP family of plating chemistries.

About DuPont Electronics & Industrial

DuPont Electronics & Industrial is a global supplier of new technologies and performance materials serving the semiconductor, circuit board, display, digital and flexographic printing, healthcare, aerospace, industrial and transportation industries. From advanced technology centers worldwide, teams of talented research scientists and application experts work closely with customers, providing solutions, products and technical service to enable next-generation technologies.

About DuPont
DuPont (NYSE: DD) is a global innovation leader with technology-based materials, ingredients and solutions that help transform industries and everyday life. Our employees apply diverse science and expertise to help customers advance their best ideas and deliver essential innovations in key markets including electronics, transportation, construction, water, health and wellness, food, and worker safety. More information can be found at http://www.dupont.com/.

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Zynq MPSoC Security 1: Introduction of Boot Time Security

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The increasing ubiquity of Xilinx® devices makes protecting the intellectual property (IP) within them as important as protecting the data processed by the device. Secure booting through the latest authentication methods is supported to prevent unauthorized or modified code from being run on Xilinx devices, and to make sure that only authorized programs access the images for loading various encryption techniques.

In a Zynq® UltraScale+™ MPSoC device, the secure boot is accomplished by using the hardware root of trust boot mechanism, which also provides a way to encrypt all of the boot or configuration files. This architecture provides the required confidentiality, integrity, and authentication to host the most secure of applications.

Zynq UltraScale+ MPSoCs has an AES-GCM hardware engine that supports confidentiality of your boot images and can also be used in post-boot to encrypt and decrypt user data.

The Zynq UltraScale+ MPSoC hardware root of trust is based on the RSA-4096 asymmetric authentication algorithm in conjunction with SHA-3/384. There are two key pairs used in the Zynq UltraScale+ MPSoC, and consequently two public key types: the primary public key (PPK) and the secondary public key (SPK).

AES Encryption:

AES is a symmetric key encryption technique; it uses the same key for encryption and decryption. The key used to encrypt a boot image should be available on the device for the decryption process while the device is booting with that boot image. Generally, the key is stored either in eFUSE or BBRAM, and the source of the key can be selected during boot image creation through BIF attributes. ZynqMP allows you to store the key in three forms – plain text key (Red key), obfuscated key (Gray key) and encrypted key (Black key). 

Encryption process:

The boot image partitions are encrypted based on the user-provided encryption commands and attributes in the BIF file. The Bootgen tool is used to encrypt the partitions and the .bif file is input to it.

savula_0-1631055883731.png

Figure: Encryption Process

Decryption Process:

For Xilinx SoC devices, the BootROM and the FSBL decrypt partitions during the booting cycle. The BootROM reads the FSBL from flash, decrypts, loads, and hands off the control. After the FSBL starts executing, it reads the remaining partitions, decrypts, and loads them. The AES key needed to decrypt the partitions can be retrieved from either eFUSE or BBRAM.

savula_1-1631055883735.png

Figure: Decryption process

Key Management:

The AES crypto engine has access to a diverse set of key sources. Non-volatile key sources include eFUSEs, BBRAM, a PUF key encryption key (KEK), and a family key. These keys maintain their values even when the device is powered down. Volatile key sources include an operational key and a key update register key.

Red Key:

The red key is an unencrypted key (plain-text key) and can be stored in eFUSE/BBRAM. The red key is used by bootgen to encrypt the image and the ZynqMP uses the red key to decrypt the image during boot process.

Black Key:

The black key is an AES key encrypted with the Key Encryption Key (KEK) generated by the Physical Unclonable Function (PUF) module of the ZynqMP SoC. It can be stored in the eFUSE/boot header of the created image.

Gray/Obfuscated Keys:

The obfuscated key is an AES key encrypted (obfuscated) with the family key of the ZynqMP SoC. The family key is the dedicated embedded key in the device and the same key is used on all devices within a device family. The Obfuscated key can be stored in eFUSE/boot header of the image.

Operational Key:

The OP key is a register that holds the key decrypted from the secure header of the boot image. A good key management practice includes minimizing the use of secret or private keys. This can be accomplished using the operational key option enabled in Bootgen.

When enabled, the encrypted secure header in the FSBL will contain nothing more than the OP key, which is user specified, and the initialization vector (IV) needed for the first block of the configuration file. The result is that the AES key stored on the device, in either the BBRAM or eFUSEs, is only used for 384 bits, which significantly limits its exposure to side channel attacks.

savula_2-1631055883740.png

Figure: Operational key

Rolling Keys:

The AES_GCM rolling keys feature represent the entire encrypted image in terms of smaller AES encrypted blocks/modules. Each module is encrypted using its own unique key. The initial key is stored at the key source on the device, while keys for each successive module are encrypted (wrapped) in the previous module.

RSA Authentication:

RSA is an asymmetric algorithm, meaning that the key to verify is not the same key used to sign. A pair of keys are needed for authentication. Signing is done using Secret Key/ Private Key and Verification is done using a Public Key.

In Xilinx SoCs, two pairs of public and secret keys are used – primary and secondary. The function of the primary public/secret key pair is to authenticate the secondary public/secret key pair. The function of the secondary key is to sign/verify partitions.

Singing:

The Bootgen signs partitions using the Secret key. The signing process is described in the following steps:

  • PPK and SPK are stored in the Authentication Certificate (AC).
  • SPK is signed using PSK to get the SPK signature which is also stored as part of the AC.
  • Partition is signed using SSK to get Partition signature which is populated in the AC.
  • The AC is appended or prepended to each partition that is opted in for authentication depending on the device.
  • PPK is hashed and stored in eFUSE.

Verification:

In the device, the BootROM verifies the FSBL, and either the FSBL or U-Boot verifies the subsequent partitions using the Public key.

  1. Verify PPK: This step establishes the authenticity of the primary key, which is used to authenticate the secondary key
    1. PPK is read from the AC in the boot image
    2. Generate the PPK hash
    3. The hashed PPK is compared with the PPK hash retrieved from the eFUSE
    4. If they are the same, then the primary key is trusted. Otherwise secure boot will fail
  2. Verify secondary keys: This step establishes the authenticity of the secondary key, which is used to authenticate the partitions
    1. The SPK is read from the AC in the boot image
    2. Generate the hashed SPK
    3. Get the SPK hash, by verifying the SPK signature stored in the AC using PPK
    4. Compare the hashes from step (b) and step (c)
    5. If they are the same, then the secondary key is trusted. Otherwise secure boot will fail
  3. Verify partitions: This step establishes the authenticity of the partition which is being booted
    1. The partition is read from the boot image
    2. Generate the hash of the partition
    3. Get the partition hash by verifying the Partition signature stored in the AC using SPK
    4. Compare the hashes from step (b) and step (c)
    5. If they are the same, then the partition is trusted. Otherwise secure boot will fail

References: 

1. https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf

2. https://www.xilinx.com/support/documentation/user_guides/ug1137-zynq-ultrascale-mpsoc-swdev.pdf

3. https://www.xilinx.com/support/documentation/sw_manuals/xilinx2021_1/ug1283-bootgen-user-guide.pdf

4. https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841708/Zynq+Ultrascale+MPSoC+Security+Features

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Source: https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Zynq-MPSoC-Security-1-Introduction-of-Boot-Time-Security/ba-p/1285779

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Floorplanning Tips

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When it comes to floorplanning, the old adage “less is more” is fitting. A design floorplan is broadly defined as a set of physical constraints used to control how logic is placed in the die.  A good floorplan can help reduce routing congestion and improve the quality of timing results (QoR) that Vivado can achieve for a given design. 

Conversely, a poor floorplan can have the opposite effect.  Before creating any type of floorplan, designers should consult the excellent discussion on the topic found in chapter 8 of (UG906). This blog post is offered as a supplement to the information in the user guide.

Pblock Boundaries

Pblock boundaries allow you to leverage clock regions boundaries to define the size of the pblock as opposed to using ranges of SLICEs, BRAMs, DSPs, etc.  This can help limit clock skew and help with overall clock placement of the design. 

Below are some examples of resizing pblocks:

create_pblock pblock_cr0
resize_pblock pblock_cr0 -add CLOCKREGION_X0Y0:CLOCKREGION_X0Y0

create_pblock pblock_slr1
resize_pblock pblock_slr1 -add SLR1

Users can use clock region or SLR based floorplans, even if they want to exclude certain types of sites from the pblock. 

The following Tcl command demonstrates how to resize a pblock to remove the DSP sites from the clock region pblock created in the previous example.

resize_pblock pblock_cr0 -remove [get_sites DSP* -of [get_clock_regions X0Y0]]

Pblock boundaries are soft by default, which means that Vivado can move cells outside of the pblock in later placer stages if it helps with timing closure.

In some cases, it makes sense to harden the boundary to prevent this behavior.  This can be accomplished by setting the IS_SOFT property of the pblock to FALSE.  This can be useful when trying to control clock placement.

set_property IS_SOFT FALSE [get_pblocks pblock_slr1]

Clocking Architecture

Clocking plays a large role in determining how a design is placed and routed. 

Understanding the clocking resources available in the device family that the design is targeted toward is an essential prerequisite to floorplanning. 

Issues that commonly arise include:

  • Re-using outdated clocking that was optimal for a previous device family, but is not the best option for the current device family (Missing out on MBUFGCE_DIV, BUFGCE_DIV, etc…)
  • Using more clocking resources than are needed when fewer would suffice
  • Overlooking clock uncertainty caused by jitter

Designers should always optimize the clocking architecture of their designs. To do so, it is important to have a good understanding of all the clocks used in their designs.  Here is a useful Tcl command that offers a quick shortcut to visualize all of the clocks used in a design.

show_schematic  [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ CLOCK.*.* } ]

2021-09-08 10_14_35-xcoapps67_1 (xcoapps67_1 (jbieker)) - VNC Viewer.jpg

A much more detailed picture of each individual clock and the distribution of loads is available in the clock utilization report (report_clock_utilization).  Reviewing the load placement of each clock can help designers see how Vivado places the logic connected to each clock.  Consider the device cell placement summary for a global clock below.

Note that a small number of loads (70) have been placed in SLR1 while the clock root and driver is placed adjacent to the transceiver in the upper left corner of the die denoted with (R) and (D).  Further note that the horizontal programmable delay requires 7 taps to balance the clock skew.

2021-09-08 12_48_33-xcoapps67_1 (xcoapps67_1 (jbieker)) - VNC Viewer.jpg

One floorplanning approach could be to restrict the placement of the loads of the clock with a hard pblock. 

For example:

create_pblock slr2_3
resize_pblock slr2_3 -add SLR2:SLR3
set_property IS_SOFT FALSE [get_pblocks slr2_3]
add_cells_to_pblock slr2_3 [set pb_cells [all_registers -clock <clock_name> ]]

One caveat to this approach is that designers need to remember that dual port BRAMs/URAMs have two clocks.  As such, the all_registers command will collect memories where the clock is connected to either of the clock inputs. 

However, it is a simple matter to remove any group of objects from a pblock once they have been assigned using remove_cells_from_pblocks. 

Here is an example showing how to remove the BRAMs/URAMs from the pblock above.

remove_cells_from_pblock slr2_3 [filter $pb_cells {PRIMITIVE_TYPE =~ BLOCKRAM.*.*}]

Hierarchical Floorplanning

Use KEEP_HIERARCHY on sizable modules that will be floorplanned.  The KEEP_HIERARCHY attribute forces the synthesis tool to retain the logical interface and prevent cell merging with other instances.

This important guidance is often overlooked, particularly when a single module is instantiated multiple times in a loop. As a result, data and control signals are often shared between instances of the same module.  This leads to difficulty when trying to physically isolate modules because they are not logically isolated. 

The image below shows a single module that has been instantiated twice without the use of KEEP_HIERARCHY during synthesis.  Note the high degree of interconnect between the modules which serves to pull the modules closer together during placement.  Even though the two modules come from the same piece of RTL, the synthesized result is not a good fit for floorplanning because of the significant interconnect between the two.

no_keep_hier.jpg

Here is what the same two modules look like when they are logically isolated with KEEP_HIERARCHY attributes.

The result is much cleaner and the two modules can now be physically isolated with hierarchical floorplanning constraints if needed.  A side benefit of using KEEP_HIERARCHY is that the placer can often physically isolate the modules without the assistance of a floorplan.

keep_hier.jpg

It is easy to create a hierarchical floorplan of modules in a design.  The required XDC constraints (or Tcl commands) are straightforward and can be accomplished in three lines. 

Here is an example of constraining a module to a single clock region.

create_pblock pblock_1
resize_pblock pblock_1 -add CLOCKREGION_X0Y0:CLOCKREGION_X0Y0
add_cells_to_pblock pblock_1 [get_cells [list module_A module_B module_C]]

Some designers prefer to use the hierarchical cell property USER_SLR_ASSIGNMENT instead of using pblocks.  This approach is fine, but it is important to note that the USER_SLR_ASSIGNMENT property is designed for hierarchical cells, not for leaf level cells such as flip flops, LUTs, DSPs, etc. 

Users should commit to either using SLR-based pblocks *OR* USER_SLR_ASSIGNMENT properties, but not both.  Mixing the two techniques only leads to confusion.

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Source: https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Floorplanning-Tips/ba-p/1286261

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Three DuPont Technologists Recognized with Industry Honors for…

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“We are incredibly proud of the achievements of all three of these individuals, and the passionate spirit that they bring to our teams in driving the development of novel materials and continued enhancements for semiconductor fabrication.”

DuPont Electronics & Industrial today announced that three of its scientists in its Semiconductor Technologies business group have recently been honored with industry recognitions for their work in developing materials for advanced semiconductor fabrication.

In July 2021, Emad Aqad, Ph.D., was recognized with the 2020-2021 Asian American Most Promising Engineer of the Year Award. The Asian American Engineer of the Year Award (AAEOY) program is a recognition established to honor the most distinguished US-based professionals for their leadership, technical achievements and public service. The AAEOY program is hosted by the Chinese Institute of Engineers/USA (CIE/USA).

Dr. Aqad is a principal investigator based at the DuPont Electronics & Industrial site in Marlborough, Massachusetts. Dr. Aqad was nominated by his peers for his outstanding scientific contributions in developing sophisticated lithographic materials for semiconductor fabrication, including photoresists for advanced patterning technologies such as KrF, ArF and extreme ultraviolet (EUV) lithography. His expertise also extends to the design and development of spin-on carbon platforms, as well as directed self-assembly and other materials for pattern miniaturization. Numerous materials developed by Dr. Aqad have been successfully commercialized, including innovations which have been established as the process-of-record for leading integrated circuit fabricators at advanced technology nodes.

In August 2021, Alaaeddin Alsbaiee, Ph.D., was named to the 2021 Chemical & Engineering News’ (C&EN) Talented 12. The C&EN Talented 12 program recognizes early career scientists who are making their mark on industry and global challenges. As part of this recognition, Dr. Alsbaiee has been invited to speak at the C&EN Talented 12 Symposium on September 28, where he will present a talk titled, “Imagination Sparks Creativity in Polymer Science.”

Dr. Alsbaiee is a research investigator based at the DuPont Electronics & Industrial site in Newark, Delaware. Dr. Alsbaiee is part of a team developing novel polishing pad technology for chemical mechanical planarization (CMP) processes. Continued innovations in CMP pads allow customers to meet diverse application and performance requirements for all technology nodes.

Most recently, Jae Hwan Sim, Ph.D., was named an International Fellow of the Industrial & Engineering Chemistry (I&EC) Division of the American Chemical Society (ACS). The I&EC Division of ACS has a focus on helping individuals convert science into commercially relevant products. I&EC Fellowships recognize scientists and engineers who have made a significant contribution to the chemical industry.

Dr. Sim is a principal investigator in the Litho Technologies business, based at the DuPont Korea Technology Center in Hwaseong, Korea. Dr. Sim was recognized for his work in developing a wide array of advanced technologies including novel gap-filling, bottom antireflective coating (BARC), and EUV lithography underlayer materials to enable complex, high-resolution lithographic processes. He is a named inventor on over 15 granted patents and has contributed to the successful commercialization of over 10 new product offerings for the fabrication of advanced semiconductor devices.

“These prestigious third-party recognitions are a true testament to the caliber of our talent globally and their wide-reaching industry impact,” said Cathie Markham, vice president of R&D, DuPont Electronics & Industrial. “We are incredibly proud of the achievements of all three of these individuals, and the passionate spirit that they bring to our teams in driving the development of novel materials and continued enhancements for semiconductor fabrication.”

About DuPont Electronics & Industrial

DuPont Electronics & Industrial is a global supplier of new technologies and performance materials serving the semiconductor, circuit board, display, digital and flexographic printing, healthcare, aerospace, industrial and transportation industries. From advanced technology centers worldwide, teams of talented research scientists and application experts work closely with customers, providing solutions, products and technical service to enable next-generation technologies.

About DuPont

DuPont (NYSE: DD) is a global innovation leader with technology-based materials and solutions that help transform industries and everyday life. Our employees apply diverse science and expertise to help customers advance their best ideas and deliver essential innovations in key markets including electronics, transportation, construction, water, healthcare and worker safety. More information about the company, its businesses and solutions can be found at http://www.dupont.com. Investors can access information included on the Investor Relations section of the website at investors.dupont.com.

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09/21/21

DuPont™, the DuPont Oval Logo, and all trademarks and service marks denoted with ™, ℠ or ® are owned by affiliates of DuPont de Nemours, Inc. unless otherwise noted.

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