The Vivado Simulator provides an interactive mechanism to force a signal, wire, or register to a specified value at a specified time or period of time. You can also force values on objects to change over a period of time. This blog describes techniques to create test cases in simulation using Vivado Simulator by forcing certain data pattern on core interfaces.
When designing a system with the Versal™ ACAP Integrated Block for PCI Express IP, designers might run into issues where the system halts due to a certain incoming packet or incorrect toggling of signals. To debug such issues in hardware could be difficult and time consuming as this would require debugging using tools such as ChipScope.
The easiest option to debug is to try to reproduce the issue in simulation, if possible, by writing a specific testbench. The problem with this approach is that the user will need to invest a significant amount of time to write a comprehensive testbench code. Vivado Simulator’s ‘force’ command feature can be used to reproduce issues by injecting packets and toggling signals at any specified time.
The Versal ACAP Integrated Block for PCI Express IP comes with an example design that can be opened by right clicking the ‘Open Example Design’ option on the instantiated IP in the ‘Sources’ Window. The default simulator used to simulate the example design is Vivado Simulator as shown below in ‘settings’.
There are two types of example design that can be generated for Versal ACAP Integrated Block for PCI Express IP in Vivado – BMD and PIO. The default example design is PIO which has two modes – Address Align Mode and Dword Align Mode. (See PG343)
- For Address Align Mode, the PIO design implements an 8192 byte target space in ACAP block RAM, behind the Endpoint for PCIe. This 32-bit target space is accessible through single Dword I/O Read, I/O Write, Memory Read 64, Memory Write 64, Memory Read 32, and Memory Write 32 TLPs. The PIO design generates a completion with one Dword of payload in response to a valid Memory Read 32 TLP, Memory Read 64 TLP, or I/O Read TLP request presented to it by the core. In addition, the PIO design returns a completion without data with a successful status for an I/O Write TLP request.
- For Dword Align Mode, the PIO design implements a 2048 byte target space in ACAP block RAM. This target space and data width varies based on the AXI4-Stream interface and is equal to the width of the AXI4-Stream interface. This target space is accessible through Memory Write 32 and Memory Read 32 TLPs. The PIO generates a completion with the payload size in response to a valid Memory Read 32 TLP request from the core.
The screenshot below shows simulation waveform capture from the PIO Example Design generated for Dword Align Mode.
On the RQ interface of RP, the first packet is MWr and the second packet is MRd. These packets appear on the CQ interface of the Endpoint as shown below.
The screen capture below shows a Zoomed in capture of an MWr packet on the Root Port (RP) RQ interface:
The screenshot below shows a Zoomed in capture of an MRd packet on the RP RQ interface:
The screenshot below shows a Zoomed in capture of an MRd packet on the RP RQ interface:
Similarly, Zoomed in views MWr and MRd packets on the Endpoint CQ interface are shown below.
Memory Write (MWr):
m_axis_cq_tuser:
Memory Read (MRd):
m_axis_cq_tuser:
Vivado Simulator’s ‘force’ command can be used to send the second Memory Write packet after the Memory Read packet.
This can be done by adding the following command in a Tcl file:
add_force {/board/RP/s_axis_rq_tlast} {1 355.260us} {0 355.264us}
add_force {/board/RP/s_axis_rq_tdata} -radix hex {00000000000000000000000000000000000000000000000000000000000000000f0e0d0c0b0a090805060708010203040101a00900af08010000000000000010 355.260us} {0 355.264us}
add_force {/board/RP/s_axis_rq_tuser} -radix hex {00000000000000000000000000015540000000f410000f 355.260us} {0 355.264us}
add_force {/board/RP/s_axis_rq_tkeep} -radix hex {001f 355.260us} {0 355.264us}
add_force {/board/RP/s_axis_rq_tvalid} {1 355.260us} {0 355.264us}
The location of the Tcl file is added in the xsim.simulate.tcl.post* field in the Simulation Settings GUI as shown below:
The screenshot below shows the second MWr packet at 355.260 ns as a result of the added force commands.
Below is a Zoomed in view of the force command generated MWr packet on the RP RQ interface:
The same packet on the EP CQ interface is shown below:
The above is just an illustration on the capability of Vivado Simulator ‘force’ command to debug Versal ACAP Integrated Block for PCI Express issues by reproducing custom design hardware issue in simulation. Some of the other scenarios that can be used for debug using ‘force’ commands are:
- Generate multiple MWr packets to read and write from the Endpoint.
- Generate packets upstream from the Endpoint to the Root Port.
- Inject erroneous packet into the IP and observe the IP behavior to mimic with the hardware behavior
- Force assertion or deassertion of signals like ‘tready’ and ‘tvalid’ for test purpose
Notes:
- Although the Versal ACAP Integrated Block for PCI Express IP has been referred to above, similar techniques can be applied to any other IP cores and custom designs.
- To learn about ‘force’ command usage in ModelSim, see (Xilinx Answer 53776)
For more information on Vivado Simulator ‘force’ commands, see (UG900).
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