Week In Review: Design, Low Power
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Week In Review: Design, Low Power

DRAM verification; MIPI A-PHY doubles downlink data rate; EDA revenue up; flexible hybrid electronics projects.

The post Week In Review: Design, Low Power appeared first on Semiconductor Engineering.

Week In Review: Design, Low Power

Tools & design
EDA industry revenue increased 7.1% year-over-year from $2.95 billion to $3.46 billion in Q3 2021, according to the ESD Alliance. “Geographically, all regions reported double-digit growth, with product categories CAE, Printed Circuit Board and Multi-Chip Module, SIP, and Services also showing double-digit growth,” said Walden C. Rhines, Executive Sponsor of the SEMI Electronic Design Market Data report. The IP segment saw the largest increase, with revenue increasing 30.6% year-over-year and the four-quarters moving average increasing 22.1%. Tracked companies employed 51,182 people globally in Q3 2021, an 8.7% increase over the Q3 2020 headcount and up 2.4% compared to Q2 2021.

The MIPI Alliance published MIPI A-PHY v1.1, the next version of the automotive SerDes physical-layer interface. Version 1.1 doubles the maximum available downlink data rate from 16 Gbps to 32 Gbps by adding support for Star Quad (STQ) cables that provide dual differential pairs of conductors within a single shielded jacket. It also adds optional PAM4 encoding for A-PHY downlink gears G1 and G2, with data rates of 2 Gbps and 4 Gbps, respectively. The version also adds a faster uplink gear with an available data rate of up to 200 Mbps, twice the rate of the existing uplink gear, providing more bandwidth for command and control of automotive peripherals.

Microchip deployed Cadence’s Palladium Z2 Enterprise Emulation Platform for the development of its next generation ASIC products targeting high performance and scalable SoC solutions for data centers. “The common compile flow offered by the Palladium and Protium dynamic duo, combined with unified peripherals, allows us to distribute verification workloads freely between the two platforms. With the new Palladium Z2 platform, the 2X higher gate capacity and 1.5X faster runtime performance allowed us to implement our largest multi-chip systems efficiently to meet our challenging time-to-market and quality requirements,” said Riad Ben-Mouhoub, senior technical staff engineer at Microchip.

Siemens Digital Industries Software and UMC made PDKs available for the foundry‘s 110nm and 180nm BCD technology platforms. The PDKs are optimized for Siemens EDA’s Tanner custom design flow software.

Worldwide semiconductor revenue increased 25.1% in 2021 to total $583.5 billion, according to preliminary results by Gartner. “As the global economy bounced back in 2021, shortages appeared throughout the semiconductor supply chain, particularly in the automotive industry,” said Andrew Norwood, research vice president at Gartner. “The resulting combination of strong demand as well as logistics and raw material price increases drove semiconductors’ average selling price higher (ASP), contributing to overall revenue growth in 2021.” Norwood also noted strong unit production in the 5G smartphone market.

Memory & storage
Cadence debuted a new DRAM verification solution. It provides IP-level verification through PHY VIPs and memory models with a path to SoC-level verification with the Cadence System VIP solution, including the System Performance Analyzer, System Traffic Libraries and System Scoreboard, with built-in integration and content for DRAM interfaces. It also includes a verification plan linked to a specification, including JEDEC, DFI and PHY, comprehensive coverage models, and a test suite to ensure compliance with the interface specification. “DRAM memory verification requires unique methods to ensure that all timing, power and throughput requirements are met in various conditions,” said Paul Cunningham, senior vice president and general manager, R&D, in the System & Verification Group at Cadence.

Fujitsu Semiconductor unveiled 8Mbit FRAM MB85RQ8MLX with Quad SPI interface. A non-volatile memory that operates at a low power supply voltage from 1.7V to 1.95V, the new Quad SPI interface FRAM achieves 54MB/s data reading/writing speed with four I/O pins and 108MHz operating frequency in high-temperature environments up to 105 degrees C. It targets applications such as HPC, data center, and industrial computing.

Infineon added development tools supporting the SEMPER NOR Flash family of devices. The SEMPER Solutions Hub portal offers access to software development kits (SDKs) containing production-grade drivers and application code examples. Also available are hardware kits for prototyping with MCU system boards from both Infineon and third-party suppliers, MCUs and available IDEs. Supported architectures include the Infineon PSoC 6 and AURIX TC375, Raspberry Pi and NVIDIA Jetson Nano.

Kioxia launched its Universal Flash Storage (UFS) Ver. 3.1 embedded flash memory devices with 4-bit-per-cell, quadruple-level cell (QLC) technology. The new 512 GB QLC UFS PoC (Proof of Concept) devices utilize the company’s 1 Terabit BiCS FLASH 3D flash memory with QLC technology, for potential larger Terabyte scale QLC UFS density offerings in the future. It targets applications needing high density such as smartphones.

Security
The Morello program, a collaboration between Arm, University of Cambridge, and others to define and implement hardware capabilities that would provide a fundamentally more secure building block for software, hit a new milestone with the release of an SoC and demonstrator board. The boards are based on the Morello prototype architecture embedded into an Armv8.2-A processor (an adaptation of the Arm Neoverse N1 processor). The boards are being distributed to major stakeholders such as Google and Microsoft as well as to interested partners across the industry and academia via the UKRI Digital Security by Design (DSbD) initiative. “Memory safety exploits are one of the longest standing and most challenging problems in all of software security,” said David Weston, Director of Enterprise and OS Security, Microsoft. “Using core silicon architecture to eliminate whole classes of security issues with minimal performance impact has the opportunity to be transformative with massive positive impact.”

Power devices
Infineon introduced a new family of intelligent integrated half-bridges. Along with a p-channel high-side and an n-channel low-side MOSFET, MOTIX BTN99xx includes smart driver ICs fully integrated in a single package. It targets applications where low PCB consumption is critical, as well as applications that require reliability such as seat controls, electric tailgates and sliding doors, and fuel pumps.

Menlo Micro released a high-power single-pole/four-throw (SP4T) DC-to-18 GHz switch for high-power RF switching applications. Based on the company’s Ideal Switch technology, the MM5120 SP4T switch offers ultra-low insertion loss, 25W power handling, and high linearity, with a custom-designed built-in high-voltage charge pump, integrated into a miniature 5.2mm x 4.2mm LGA package.

Infineon debuted EiceDRIVER 2ED4820-EM, a smart gate driver with SPI interface. It can tolerate negative voltages at Vbat down to -90 V and voltages up to +105 V and includes a current sense amplifier for high or low-side measurement. It targets 48 V battery systems.

Halo Microelectronics listed on the STAR Market in the Shanghai Stock Exchange at an issue price of RMB 33.57 (~$5.29) per share. Halo Microelectronics develops analog and power management integrated circuits. “We’re excited to lead the industry in the energy efficient battery and power management solutions. I’m proud of our teams’ accomplishment to reach this great milestone,” said David Nam, CEO of Halo Microelectronics.

Quantum computing
The first quantum computer in Europe with more than 5,000 qubits launched at Forschungszentrum Jülich. The new system, built with D-Wave, is an annealing quantum computer, which is suited to optimization problems in industrial applications. “We’re also looking at ways to integrate the new system into our supercomputing infrastructure. At that time, to the best of our knowledge, this would be the first instance of a quantum computer working directly with a supercomputer,” said Prof. Thomas Lippert, director of the Jülich Supercomputing Centre. “This is made possible because the quantum annealer has over 5,000 qubits and is therefore big enough to help with application-related problems that are typically calculated on supercomputers.” Jülich and D-Wave Systems also debuted a cloud-based quantum service.

Funding
SEMI FlexTech awarded $5 million in funding for new R&D projects focused on flexible hybrid electronics (FHE). The projects include: optimization of pastes, inks, and coating for additive manufacture of higher performance FHE and direct writing in 3D printed circuit structures (ACI Materials); in situ monitoring and machine learning control of electrohydrodynamic inkjet printing (University of Washington); AI to increase the reliability of printed electronics using optical and ultrasonic metrologies and acoustic emissions (Cornell University); a bio-inspired soft robot for assisting a human operator in performing inspection maintenance and repair in highly confined spaces inside industrial and defense facilities (GE Research); and development of a high-power (≥1.2kV), low-profile, low-inductance silicon carbide power module using conformable direct write interconnects and packaging (GE Research).

South Korea’s Ministry of Science and ICT will invest 402.7 billion won ($337.4 million) in the development of processing-in-memory (PIM) chips, reports The Korea Herald. The funds will also be used to support commercialization of hyperscale AI by providing vouchers for small- and medium-sized firms and universities to use the hyperscale AI of large companies such as Naver, Kakao, and LG. Other efforts will include testing performance of AI processors and software for AI chip development.

Source: https://semiengineering.com/week-in-review-design-low-power-180/

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