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Von Neumann Is Struggling




In an era dominated by machine learning, the von Neumann architecture is struggling to stay relevant.

The world has changed from being control-centric to one that is data-centric, pushing processor architectures to evolve. Venture money is flooding into domain-specific architectures (DSA), but traditional processors also are evolving. For many markets, they continue to provide an effective solution.

The von Neumann architecture for general-purpose computing was first described in 1945 and stood the test of time until the turn of the Millennium. The paper John von Neumann wrote described an architecture where data and programs are both stored in the same address space of a computer’s memory — even though it was actually an invention of J. Presper Eckert and John Mauchly.

A couple reasons explain the architecture’s success. First, it is Turing Complete, which means that given enough memory and enough time, it can complete any mathematical task. Today we don’t think much about this. But back in the early days of computing, the notion of a single machine that could perform any programmed task was a breakthrough. Passing this test relies on it having random access to memory.

Second, it was scalable. Moore’s Law provided the fuel behind it. Memory could be expanded, the width of the data could be enlarged, the speed at which it could do computations increased. There was little need to modify the architecture or the programming model associated with it.

Small changes were made to the von Neumann architecture, such as the Harvard architecture that separated the data and program buses. This improved memory bandwidth and allowed these operations to be performed in parallel. This initially was adopted in digital signal processors, but later became used in most computer architectures. At this point, some people thought that all functionality would migrate to software, which would mean an end to custom hardware design.

End of an era
Scalability slowed around 2000. Then, Dennard scaling reared its head in 2007 and power consumption became a limiter. While the industry didn’t recognize it at the time, that was the biggest inflection point in the industry to date. It was the end of instruction-level parallelism. At first, it seemed as if the solution was to add additional processors. This tactic managed to delay the inevitable, but it was just a temporary fix.

“One of the problems is that CPUs are not really good at anything,” says Michael Frank, fellow and system architect at Arteris IP. “CPUs are good at processing a single thread that has a lot of decisions in it. That is why you have branch predictors, and they have been the subject of research for many years.”

But in an era of rapid change, any design that does not expect the unexpected may be severely limited. “Von Neumann architectures tend to be very flexible and programmable, which is a key strength, especially in the rapidly changing world of machine learning,” says Matthew Mattina, distinguished engineer and senior director for Arm’s Machine Learning Research Lab. “However, this flexibility comes at a cost in terms of power and peak performance. The challenge is to design a programmable CPU, or accelerator, in a way such that you maintain ‘enough’ programmability while achieving higher performance and lower power. Large vector lengths are one example. You’re amortizing the power cost of the standard fetch/decode portions of a CPU pipeline, while getting more work done in a single operation.”

Fig. 1: The von Neumann architecture, first described in the 1940s, has been the mainstay of computing up until the 2000s. Data and programs are both stored in the same address space of a computer’s memory. Source: Semiconductor Engineering

Accelerators provide a compromise. “Accelerators, serve two areas,” says Arteris’ Frank. “One is where you have a lot of data moving around, where the CPU is not good at processing it. Here we see vector extensions going wider. There are also a lot of operations that are very specific. If you look at neural networks, where you have non-linear thresholding and you have huge matrix multiplies, doing this with a CPU is inefficient. So people try to move the workload closer to memory, or into specialized function units.”

To make things even more complicated, the nature of data has changed. More of it is temporal. The temporal aspects of data were first seen with audio and video. But even a couple decades ago, a single computer could keep up with the relatively slow data rates of audio. Video has presented much greater challenges, both for processing and memory.

The memory bottleneck
Memory access is expensive in terms of time and energy. Caches address this problem by exploiting data locality. “Most silicon designs use various technologies for reducing power consumption,” says Anoop Saha, market development manager for Siemens EDA. “Improving memory accesses is one of the biggest bang-for-the-buck architecture innovations for reducing overall system-level power consumption. That is because an off-chip DRAM access consumes almost a thousand times more power than a 32-bit floating point multiply operation.”

Ever-more complex caching schemes have been developed since then in an attempt to bring the memory closer to the processor. But accessing a cache still consumes 200X the power compared with the same variable being stored in a register.

Put simply, memory has become the limiter. “For some applications, memory bandwidth is limiting growth,” says Ravi Subramanian, vice president and general manager for Siemens EDA. “One of the key reasons for the growth of specialized processors, as well as in-memory (or near-memory) computer architectures, is to directly address the limitations of traditional von Neumann architectures. This is especially the case when so much energy is spent moving data between processors and memory versus energy spent on actual compute.”

The rapid emergence of AI/ML is forcing change in the memory architecture. “The processors may be custom, but you need the SRAM to be local,” says Ron Lowman, strategic marketing manager for IoT at Synopsys. “For AI applications, you want to execute and store as much of the weights and coefficients as close to the MACs as possible. That is what eats up the power consumption. Multi-port memories are very popular for AI. This means you can parallelize reads and writes when you are doing the math. That can cut the power in half.”

This kind of change comes with a large penalty. “The challenge is that in the past, people had a nice abstract model for thinking about computing systems,” says Steven Woo, fellow and distinguished inventor at Rambus. “They never really had to think about memory. It came along for free and the programming model just made it such that when you did references to memory, it just happened. You never had to be explicit about what you were doing. When new kinds of memories enter the equation, you have to get rid of the very abstract view that we used to have to make them really useful.”

This needs to change, however. “Programmers will have to become more aware of what the memory hierarchy looks like,” Woo says. “It is still early days, and the industry has not settled on a particular kind of model, but there is a general understanding that in order make it useful, you have to increase the understanding about what is under the hood. Some of the programming models, like persistent memory (PMEM), call on the user to understand where data is, and to think about how to move it, and ensure that the data is in the place that it needs to be.”

At the heart of AI applications is the multiply accumulate function (MAC), or dot product operation. This takes two numbers, multiplies them together and adds the result to an accumulator. The numbers are fetched from and stored to memory. Those operations are repeated many times and account for the vast majority of the time and power consumed by both learning and inferencing.

The memory needs of AI are different from those of GPUs or CPUs. “It is important to optimize the algorithm to improve data locality so as to minimize data movement,” says Siemens’ Saha. “These choices are dependent on the specific workloads that the chip is designed to run. For example, image processing accelerators use line buffers (which works on only a small sample of an image at a time), whereas a neural network accelerator uses double buffer memories (as they will need to operate on the image multiple times).”

For example, with an AI accelerator that processes layer-by-layer, it is possible to anticipate what memory contents will be required ahead of time. “While layer N is being processed, the weights for layer N+1 are brought in from DRAM, in the background, during computation of layer N,” explains Geoff Tate, CEO of Flex Logix. “So the DRAM transfer time rarely stalls compute, even with just a single DRAM. When layer N compute is done, the weights for layer N+1 are moved in a couple microseconds from a cache memory to a memory that is directly adjacent to the MACs. When the next layer is computed, the weights used for every MAC are brought in from SRAM located directly adjacent to each cluster of MACs, so the computation access of weights is very low power and very fast.”

Domain-specific architectures often come with new languages and programming frameworks. “These often create new tiers of memory and ways to cache it or move the data so that it is closer to where it needs to be,” says Rambus’ Woo. “It adds a dimension that most of the industry is not used to. We have not really been taught that kind of thing in school and it is not something that the industry has decades of experience with, so it is not ingrained in the programmers.”

Times are changing
But that may not be enough. The world is slowly becoming more conscious of the impacts of using arbitrary amounts of energy, and the ultimate damage we are doing to our environment. The entire tech industry can and must do better.

Academics have been looking at the human brain for inspiration, noting that pulsing networks are closer to the way the brain works than large matrix manipulations against a bank of stored weights, which are at the heart of systems today. Pulses fire when something important changes and does not require completely new images, or other sensor data, every time the equivalent of a clock fires. Early work shows that these approaches can be 20X to 50X more power-efficient.

Mixed-signal solutions are a strong candidate. “There are designs that are closer to mixed-signal designs that are looking at doing computation directly within the memories,” says Dave Pursley, product management director at Cadence. “They are focusing on the elimination of data movement altogether. Even if you read a lot of the academic papers, so much of the research used to be about how do you reduce the amount of computation and now we are in a phase where we are looking at the reduction in data movement or improve locality so that you don’t need such massive amounts of storage and those very costly memory accesses in terms of power.”

New computation concepts are important. “The idea is that these things that can perform multiply-accumulates for fully connected neural network layers in a single timestep,” explained Geoffrey Burr, principal RSM at IBM Research. “What would otherwise take a million clocks on a series of processors, you can do that in the analog domain, using the underlying physics at the location of the data. That has enough seriously interesting aspects to it in time and energy that it might go someplace.”

Analog may have another significant advantage over the digital systems being used today. Object detection systems in today’s automobiles often cannot handle the unexpected. “Neural networks are fragile,” said Dario Gil, vice president of AI and IBM Q, during a panel discussion at the Design Automation Conference in 2018. “If you have seen the emergence of adversarial networks and how you can inject noise into the system to fool it into classifying an image, or fooling it into how it detects language of a transcription, this tells you the fragility that is inherent in these systems. You can go from something looking like a bus, and after noise injection it says it a zebra. You can poison neural networks, and they are subject to all sorts of attacks.”

Digital fails, analog degrades. Whether that is true for analog neural networks, and whether they can be more trustworthy, remains to be seen.

There always will be an element of control in every system we create. As a result, the von Neumann architecture is not going away. It is the most general-purpose computer possible, and that makes it indispensable. At the same time, a lot of the heavy computational lifting is moving to non-von Neumann architectures. Accelerators and custom cores can do a much better job with significantly less energy. More optimized memory architectures are also providing significant gains.

Still, that is just one design tradeoff. For devices that cannot have dedicated cores for every function they are likely to perform, there are some middle ground compromises, and the market for these remains robust. The other problem is that the programming model associated with the von Neumann architecture is so ingrained that it will take a long time before there are enough programmers who can write software for new architectures.



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Manufacturing Bits: March 2




Next-gen AFM
At the recent SPIE Advanced Lithography conference, Imec, Infinitesima and others described a new metrology tool technology called a Rapid Probe Microscope (RPM).

Infinitesima has shipped its first RPM 3D system, enabling three-dimensional (3D) metrology applications for leading-edge chips. The system was jointly developed with Imec.

In the IEDM paper, Imec and Infinitesima, along with the University of Twente and the University of Bristol, described RPM. Basically, the technology makes use of tomographic atomic force microscopy (AFM) using a novel multi-probe sensing architecture.

An AFM system is a common metrology type, which includes a laser, a diode, and a cantilever with a tiny tip. In an AFM system, a tiny tip is positioned over the surface of a sample. Then, the system generates images of the sample. The goal is to find defects in the sample at the nanoscale.

“A sharp tip is raster-scanned over a surface using a feedback loop to adjust parameters needed to image a surface,” according to Nanoscience Instruments. “Traditionally, most atomic force microscopes use a laser beam deflection system where a laser is reflected from the back of the reflective AFM lever and onto a position-sensitive detector. Because the atomic force microscope relies on the forces between the tip and sample, these forces impact AFM imaging. The force is not measured directly, but calculated by measuring the deflection of the lever, knowing the stiffness of the cantilever.”

Generally, AFM systems provides detailed information at the nanoscale, but they are slow. So for years, the industry has been developing multi-probe sensing for AFMs in order to speed up the process, but there are some major challenges here.

In response, Imec, Infinitesima and others described a faster version of the technology. The technology is based on tomographic AFM or scalpel SPM (scanning probe microscopy). “The concept, often referred to as tomographic AFM or scalpel SPM, is based on use of a single-asperity nanocontact capable of sub-nm material removal, thus enabling a three-dimensional segmentation by alternating sensing and removal scans,” said Umberto Celano of Imec, Jenny Goulden of Infinitesima and others in the SPIE paper. “Here, as we aim to obtain a multiscale 3D analysis platform without compromising the high-resolution imaging, we propose a specific design, that can accomplish both accurate tip re-positioning, and a simple technique for switching and using multiple probes.”

The RPM system itself includes a scan head with a multi-probe switching system, and custom probe cassette. The custom probe cassette houses three independent AFM tips—a scalpel for tip-induced material removal; a tip for 3D profiling; and a conventional or other tip type.

The design is capable of accurate tip re-positioning. It makes use of a simple technique for switching and using multiple probes. “We show how the combined use of an interferometric detection system and strain gauge offers improved control for tip-induced material removal,” Celano, Goulden and others said in the SPIE paper.

“In summary, we have introduced a new microscope to perform tomographic sensing using scanning probe techniques. Starting from the baseline hardware of the Rapid Probe Microscope, we reported on the development of a custom scan head that is based on an in-situ, rapidly switchable, multi-probe hardware. To demonstrate the functionality of the RPM 3D, we sensed the conductive profiles in 3D for vertical poly-Si structures that mimic vertical channels of 3D NAND memory. This provides for the first time the potential to combine Scalpel SPM methodology with non-contact modes, including magnetic force microscopy of Kelvin probe force microscopy, among others,” they added. “Further development will explore non-contact modes available using this architecture and the options offered by the combined output of IDS and SG sensors for high speed, high data quality acquisition. This will drive fundamental materials research and site-specific analysis in nanoelectronics devices.”

Scanning probe lithography
Also at the SPIE event, Technische Universität Ilmenau and others presented a paper about a tip-based lithographic/metrology system that can fabricate and analyze tiny structures with high resolutions.

The system, called the Nano Fabrication Machine 100 (NFM-100), incorporates both an AFM and field-emission-scanning-probe-lithography (FESPL) in the same unit. Designed by the Technische Universitat Ilmenau, the system is manufactured by the SIOS Meßtechnik in cooperation with IMMS and nano analytic.

As stated, AFM uses a tiny tip to measure structures at the nanoscale. Scanning probe lithography, which is an R&D technology, uses tiny tips to pattern materials on structures.

With a working range up to 100mm in diameter, the NFM-100 system is an R&D tool for use in developing next-generation structures and materials with feature sizes below 10nm. The NFM-100 uses an active microcantilever with dimensions of L = 350µm x W = 140µm x T = 5µm.

In the system, the AFM can scan over long ranges at relatively high speeds. “With its large positioning range, the NFM-100 provides the possibility to analyze structures over long ranges and large areas. The NFM-100 offers an excellent accuracy and trajectory fidelity. Over a moving distance of 50mm the standard deviation perpendicular to the trajectory is as low as 1.5nm,” said Jaqueline Stauffenberg from Technische Universitat Ilmenau, in a paper at SPIE. Others contributed to the work.

Using the FESPL function, researchers pattered an SOI sample. The velocity of the microcantilever tip was set at 1 µm/s with a set point of 45 pA. With these settings, 20nm linewidths were achieved, according to researchers.

“In the future, particular focus will be placed on tip-based manufacturing on large areas with the use of the NFM-100. Here, a limiting factor is the duration of the writing process,” Stauffenberg said. “Tip-based processes are comparatively slow in fabrication and analysis, e. g. a structuring speed of about 1 µm/s on a surface of 100mm would currently result in a process time of more than 2000 hours. Due to this fact, new writing strategies have to be established and new tools have to be developed. Accordingly, tip wear is also a decisive factor. Here, the wear of the cantilever tip plays a role for the maximal permissible length of the structuring processes on large areas. However, new technologies such as parallel and multi-cantilever array applications can be used to shorten the time. Likewise, the use of diamond tips is a good way to reduce the wear of the ultra-sharp cantilever tip, which has already been proven.”

Litho books
Lithography, the art of patterning features on chips, is a complex subject. To help the industry get up to speed here, Harry Levinson, Andreas Erdmann, and Burn Lin recently discussed their latest or upcoming books on lithography.

Harry Levinson, editor-in-chief of SPIE’s Journal of Micro/Nanopatterning, Materials, and Metrology (JM3), has a new book, entitled, “Extreme Ultraviolet Lithography.” The book covers the many aspects of lithographic technology required to make EUV lithography ready for high-volume manufacturing.

Andreas Erdmann, head of computational lithography and optics at Fraunhofer IISB, discussed the materials for his upcoming book, called “Optical and EUV Lithography: A Modeling Perspective.” The book will explore various lithographic techniques for nanofabrication.

Burn Lin, a Distinguished Research Chair Professor at National Tsing Hua University and director of the Tsing Hua-TSMC Joint Research Center, discussed the material for his upcoming book, “Optical Lithography: Here is Why, Second Edition.” The book covers the image-formation physics of a lithographic system and provides an overview of the future of optical lithography and the many next-generation technologies that may enhance semiconductor manufacturing.

(For more information, contact: Daneet Steffens, public relations manager at SPIE.

The post Manufacturing Bits: March 2 appeared first on Semiconductor Engineering.

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Predicting And Avoiding Failures In Automotive Chips




Semiconductor Engineering sat down to discuss automotive electronics reliability with Jay Rathert, senior director of strategic collaborations at KLA; Dennis Ciplickas, vice president of advanced solutions at PDF Solutions; Uzi Baruch, vice president and general manager of the automotive business unit at OptimalPlus; Gal Carmel, general manager of proteanTecs‘ Automotive Division; Andre van de Geijn, business development manager at yieldHUB; and Jeff Phillips, go to market lead for transportation at National Instruments. What follows are excerpts of that conversation. To view part one of this discussion, click here.

SE: There are four major problems with data. One is there is just too much of it. If you try to cut out the amount of data using some sort of intelligent processing, you’re in danger of leaving something important behind. Second, no matter how good the data is, it probably still isn’t complete. Third, it’s usually not in a consistent format. And fourth, there’s an underlying competitive element so people are reluctant to share data. How will this play out in automotive?

Ciplickas: With regard to too much data and how to put it together in a clean way, we’ve developed a notion called a “semantic model.” Semantics are different than schema. It’s like the difference between grammar and syntax. A schema is a way to relate keys between different sources of data. But when you put semantics on top of that, although data may come from different sources, each with their own keys, you can see the data are actually very similar or the same to each other. So for different types of tools, or different types of sensors on tools, even though they they’re physically different and from different vendors, sometimes they can be treated as logically identical for analytics purposes. By identifying what’s semantically similar across all of the different sources of data, you can easily assemble data to extract useful results. By driving the notion of semantics up and down the supply chain, you get a very efficient way to put everything together for analytics and control.

Baruch: I agree. We’ve both taken different approaches to that. We grew up on the sensor side, which is much more structured. When we went into the automotive side, we had to revisit that model to bring the semantics into a descriptive layer. Also, I want to introduce the notion of event-driven. Those processes are not bounded. There may be 10, 15, or even 100 process steps when you look at the components as they are built across time. And so that idea of being able to ingest data from multiple layers — different layers, different processes, different sensors, different equipment types — and combine them all together, if you don’t have a descriptive approach you will either end up going back to your engineering team every time you need to do something, or not being able actually to fulfill that use case because you’ll get stuck in different areas. We used this approach, and it helped us move between different companies, from Tier 1s to the OEMs. By the way, both are using different languages for altogether different problems, and they still can provide a solution.

Ciplickas: Yes, there are different layers of data and different sequences that chips go through, from the wafer into the singulated die and into the packages and systems. Traceability is getting more and more important, especially in SiP. The automotive companies are dangling their feet in the water now with these advanced technologies. And if you think about the technology in an iPhone now becoming part of a car, it’s amazing the technology they can jam into a package, what they mount to a board, and how it all interacts. It will be a huge challenge to achieve automotive-level reliability. You want to be able to look at a failure from the field and quickly associate where that device came from, and what its neighbors or siblings were doing at every point along the way. From this you can build a picture of what is abnormal versus what is normal, and contrast the two to quickly get to the bottom of what’s going on. Establishing that traceability link completely through the stack is super valuable, necessary, and difficult to do. I’ve been talking with some folks at big fabless companies, and they say that as soon as you put the die into the assembly, you lose that traceability. No, you don’t have to lose that traceability. You can actually implement that in the tools. There’s formats to represent all of this, like E142, to capture component movement and operations. We participate in, as well as lead, these standards efforts to keep the format current, adding things like consumables, because you may get a bad batch of solder paste or gold wire. Bringing together data across the entire supply chain creates significant efficiencies and understanding of failures. Furthermore, once you understand the root cause of the failure and you have the traceability, you can look at what else is at risk.

Rathert: There’s another side of this loop, too. We’re talking primarily about stopping bad die or bad packages from escaping into the supply chain, but there is also plenty of potential data feed-back that could improve each of our respective domains. How do I harden my design? How do I optimize my process control plan? How do I tighten my test program? Could we can harvest both sides of this?

Carmel: There needs to be an incentive and a means to share data across the industry and across suppliers. This will help to identify, predict, and monitor issues, and offer value throughout — not to mention reach a fast resolution if something does happen. The amount of data is not as important as the quality, relevance and actionability of the data being collected. That’s why we aggregate deep data, based on real-time measurements and with a cross-stage commonality, and extrapolate the value, supplying only what is defined as pertinent. It starts with the chip vendors and Tier 1s. They can begin sharing data without compromising sensitive information. For silos to begin to organically share this data, a framework must be clearly defined, along with a common data baseline. Once those foundations are in place, liability models can be built that serve the full toolchain and push the performance, efficiency and safety envelopes at scale.

Ciplickas: We’re leading a standards effort with SEMI’s Single Device Tracking task force, using a ledger-based method to track assets — die, packages, PCBs, etc. — through the supply chain. We think it requires some type of standards effort because it’s a huge challenge to tool up the supply chain. Everyone must participate in enrolling an asset and tracking its custody and ownership as it moves from one party to another. You want to have as little data in that ledger as you can, because nobody wants to put all their manufacturing data into a public blockchain. But once you have this ledger, you know who to call in order to get more detailed data, such as through a private contract with a supplier. If you’ve got an RMA from an OEM or an automotive Tier 1 supplier, you want to understand, ‘What in the fab, at a particular process step, caused the defect? What inspection or metrology measurements do we have for this lot?’ Using the ledger, you can get back to the right supplier using the public blockchain, and then have a private discussion with them about what exactly happened. Getting everybody in the industry — including the big guns that are making the chips and spending all the money — to buy into this is taking time. So it’s a challenge, but it’s a good approach to solving this.

Phillips: There’s a whole different vector to the role that data can play for autonomous driving around the model and the modeling environment — and the combination of those used to define the behavior of the algorithm itself. Having the data from the street or from fleets being able to feed back in, in real time — whether you call that a digital twin or building some relationship between the real life data and the model, specifically in the realm of autonomous driving — is a huge opportunity. That data can be connected back into the development and testing process.

Ciplickas: It’s like real-world test cases used in software, but now you’re talking about autonomous vehicles and sensor data versus what you’re designing.

van de Geijn: We also use that for change data for subcontractors, our customers, and the customer’s customers. But getting data from fabless companies — which get data from the foundries — and matching that with data you get from wafer sort, is a problem. You need to go to different parties to get different kinds of data. You have to align it, merge it, and put your analysis on it. A lot of this is in place, so it’s very easy to use. The problem is that you have to convince your customers this is the way to go. A lot of our customers agree this is necessary, and they already are collecting data from different parties. And then we merge that together in our tools to create overviews to run analyses from all kinds of different angles, even depending on the processes you have. A CMOS chip needs different analyses than other processes. Microcontrollers may be talking to power components, each using different production processes, and different methodologies are needed to run those analyses. Now it’s a matter of having good conversations with your suppliers. But with E142 and RosettaNet, the users not only have to get the data together, they also have to know and understand what they can do. And we’re seeing more and more suppliers helping them. Then they can bring it together for startups that that have some knowledge about it.

SE: Given all of this, is it realistic to think that we can build a 5nm chip that will hold up for 18 years in the Mojave Desert, or in Fairbanks, Alaska?

van de Geijn: We will know in 18 years. If you go to Johannesburg, they will ask you if you’re planning to drive to the Kalahari Desert, because if you do, you’ll want to be able to crank open your windows by hand. You don’t want to rely on a button if there’s a lion approaching a car. So you end up with basic cars at the moment, because they don’t trust all the electronics. Yes, you have your satellite telephone with you in case you blow up your your gearbox and need help. But there are places where you’re stuck if you’re relying on electronics and something breaks. We will have to wait another 18 years before we know if something is really reliable. Here in the United States or Europe, if something happens to the car, you can take over. But I expect that for the next five years, if I go to a remote place, I will still be manually opening and closing the windows.

Rathert: That question is one that OEMs are frequently asking of us. Historically, automotive semiconductors have been developed on processes that have had years to mature. And now, suddenly, the requirements include 7nm and 5nm parts, and they just don’t have the years of maturity that a 45nm part has. So they’re asking us how we can achieve the reliability of the 45nm part in nine months instead of five years? That is the challenge. How do we cram as much learning into a couple of cycles, across all these different silos, so that we can achieve reliability faster?

Carmel: We need a data-driven approach. This process begins with a shift from identifying non-functional ECUs to predicting performance degradation, and then performing cloud-based troubleshooting while in mission mode. To achieve this, electronics need visibility so we can understand how environments, functional stress, and software impact long-term reliability, both within and in between vehicles. This can be achieved by applying deep data, which allows us to cross-correlate variations or fluctuations, and benchmark operation to the spec and guard-bands. This will help assure its functionality over 18 years. It’s not just a matter of jumping between non-failure to failure in the desert. It’s predicting what’s going to happen at the system level if you go to the desert.

Baruch: That brings up a good point, which is the notion that those chips need to be considered in the context of a higher-level system. So if a Tier 1 is developing a chip, they need to know the details about how it’s being assembled and used in the context of a system. That requires sharing of data because of the reliability aspects. But solutions also are driven by analyzing product failures, so that data also is important for outlier detection and finding anomalies. That can be applied to the system-level, as well, all the way up to the car. The combination of sharing data and applying those techniques into the higher-level components can improve reliability. You don’t want to have to wait 18 years to find out whether something is reliable.

Ciplickas: The predictive nature of having the right data is important. If you can understand why something is behaving the way it’s behaving, that can give you confidence that you’re going to achieve the goal. So when you have a failure, knowing the root cause or why there is drift, even if it’s not a failure, and having that drift correlate with variables that you understand and can control, will then give you some confidence that you’re starting to get your arms around this problem. If you look at the number of cars that will be driven in the Sahara, it’s a small fraction of the cars in the world. But there’s a bazillion other environments in which cars are going to drive. That will propel learning over the short term. Cell phones gave us confidence that we really could have this super high technology in an affordable device to do something really valuable, and that’s bleeding into ADAS systems and things like that. If you have data and predictive models, the future involves feedback loops for what happened in manufacturing. Inside the fab, there didn’t used to be as advanced process controls as we have right now, and as you add more and more advanced control loops, it will start happening in assembly fabs, on test floors and even between all of these places. Then you can take that out into the field, where you’re getting data from these systems as they operate. Building a stable feedback loop from the field is a huge challenge, for sure. But being able to connect all that data together, right back to this data-sharing thing, could then enable a predictive model that you could take action on. That’s the path to understanding long-term reliability before the 18 years is up.

Carmel: Beyond collecting the data is how you adaptively use it to define thresholds. You can extend the lifespan of electronics with continuous verification of pre-set guard-bands. The first step is generating the data, and the second step is to create the learning curves to set the correct threshold so you can balance between safety and availability.

[Uzi Baruch has since left Optimal Plus and joined proteanTecs as chief strategy officer.]

The post Predicting And Avoiding Failures In Automotive Chips appeared first on Semiconductor Engineering.

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Power/Performance Bits: March 2




Fast-charging EV battery
Electric vehicle adoption faces challenges from consumers’ range anxiety and the extended lengths of time needed to charge a car’s battery. Researchers at Pennsylvania State University are trying to address this by developing lithium iron phosphate EV batteries that have a range of 250 miles with the ability to charge in 10 minutes. It also is expected to have a lifetime 2 million miles.

“We developed a pretty clever battery for mass-market electric vehicles with cost parity with combustion engine vehicles,” said Chao-Yang Wang, chair of mechanical engineering, professor of chemical engineering, professor of materials science and engineering, and director of the Electrochemical Engine Center at Penn State. “There is no more range anxiety and this battery is affordable.”

Key to the battery’s quick charging is its self-heating ability. The battery uses a thin nickel foil with one end attached to the negative terminal and the other extending outside the cell to create a third terminal. Once electrons flow it rapidly heats up the nickel foil through resistance heating and warm the inside of the battery. When the battery’s internal temperature is 140 degrees F, the switch opens and the battery is ready for rapid charge or discharge.

Because of the fast charging, energy density was of less importance and lower cost materials could be used. The cathode is lithium iron phosphate, without expensive cobalt, while the anode is very large particle graphite. A low-voltage electrolyte was also used. The researchers also expect it to be safer, without concerns about uneven deposition of lithium on the anode, which can cause lithium spikes and battery failure.

“This battery has reduced weight, volume and cost,” said Wang. “I am very happy that we finally found a battery that will benefit the mainstream consumer mass market.”

DNA origami nanowires
Researchers from Bar-Ilan University, Ludwig-Maximilians-Universität München, Columbia University, and Brookhaven National Laboratory are using DNA origami, a technique that can fold DNA into arbitrary shapes, as a way to create superconducting nanostructures.

The DNA origami nanostructures are comprised of two major components, a circular single-strand DNA as the scaffold, and a mix of complementary short strands acting as staples that determine the shape of the structure.

“In our case, the structure is an approximately 220-nanometer-long and 15-nanometer-wide DNA origami wire,” said Lior Shani, of Bar-Ilan University. “We dropcast the DNA nanowires onto a substrate with a channel and coat them with superconducting niobium nitride. Then we suspend the nanowires over the channel to isolate them from the substrate during the electrical measurements.”

The team said the DNA origami technique can be used to fabricate superconducting components that can be incorporated into a wide range of architectures and that are not possible to construct with conventional fabrication techniques.

“Superconductors are known for running an electric current flow without dissipations,” said Shani. “But superconducting wires with nanometric dimensions give rise to quantum fluctuations that destroy the superconducting state, which results in the appearance of resistance at low temperatures.”

However, the group was able to use a high magnetic field to suppress these fluctuations and reduce about 90% of the resistance.

“This means that our work can be used in applications like interconnects for nanoelectronics and novel devices based on exploitation of the flexibility of DNA origami in fabrication of 3D superconducting architectures, such as 3D magnetometers,” continued Shani.

Tiling nanosheets
Nanosheets hold potential for making transparent and flexible electronics, optoelectronics, and power harvesting devices. However, current methods of tiling nanomaterials such as titanium dioxide can be time-consuming, expensive, and wasteful. Researchers at Nagoya University and the National Institute for Materials Science in Japan propose a simpler one-drop approach to tiling nanosheets in a single layer.

“Drop casting is one of the most versatile and cost-effective methods for depositing nanomaterials on a solid surface,” said Minoru Osada, a materials scientist at Nagoya University. “But it has serious drawbacks, one being the so-called coffee-ring effect: a pattern left by particles once the liquid they are in evaporates. We found, to our great surprise, that controlled convection by a pipette and a hotplate causes uniform deposition rather than the ring-like pattern, suggesting a new possibility for drop casting.”

The team’s process involves dropping a solution containing 2D nanosheets with a simple pipette onto a substrate heated on a hotplate to a temperature of about 100°C, followed by removal of the solution. This causes the nanosheets to come together in about 30 seconds to form a tile-like layer.

They found that the nanosheets were uniformly distributed over the substrate, with limited gaps. The researchers noted this is likely a result of surface tension driving how particles disperse, and the shape of the deposited droplet changing as the solution evaporates.

The process was used to deposit particle solutions of titanium dioxide, calcium niobate, ruthenium oxide, and graphene oxide. A variety of substrates were used, including silicon, silicon dioxide, quartz glass, and polyethylene terephthalate (PET) in different sizes and shapes. Surface tension and evaporation rate could be controlled by adding a small amount of ethanol to the solution.

The method was also used to deposit multiple layers of tiled nanosheets, creating functional nanocoatings with conducting, semiconducting, insulating, magnetic, or photochromic features. “We expect that our solution-based process using 2D nanosheets will have a great impact on environmentally benign manufacturing and oxide electronics,” said Osada.

The post Power/Performance Bits: March 2 appeared first on Semiconductor Engineering.

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