The ILA core can be configured at core generation or insertion time to have advanced trigger capabilities that include the following features:

• Trigger state machine (TSM) consisting of up to 16 states.
• Each state can consist of one-, two-, or three-way conditional branching.
• Up to four counters can be used in a trigger state machine program to keep track of multiple events.
• Up to four flags can be used in a trigger state machine program to indicate when certain branches are taken.
• The state machine can execute “goto”, “trigger”, and various counter and flag related actions.

If the ILA core in the design that is running in the hardware device has advanced trigger capabilities, the advanced trigger mode features can be enabled by setting the Trigger mode control in the ILA Properties window of the ILA Dashboard to ADVANCED_ONLY or ADVANCED_OR_TRIG_IN.

For more information on using the ILA Advanced Trigger Features, see (UG908).

This blog illustrates how the ILA advanced Trigger feature can be used to debug designs with the Versal™ ACAP Integrated Block for PCI Express IP. The same approach could be used for debugging any other Xilinx PCI Express IP cores or any designs.

Versal ACAP Integrated Block for PCI Express IP Example Design

Generate the Versal ACAP Integrated Block for PCI Express IP by configuring the required IP parameters in the core configuration GUI. Right click on the IP and then click on ‘Open Example Design’ to generate the example design. The example design opens in a separate Vivado Project as shown below.

Open the design_ep_i block diagram and add ‘Debug’ on the signals that you want to probe.

In the example design that was created for this blog, the ‘Debug’ was added on the following signals (signals with green bug icon):

Save the project and regenerate the output products for design_ep_i.

After synthesizing the design, open the synthesized design and click on ‘Set up Debug‘.

Select the nets below to debug:

Make sure to select the ‘Advanced Trigger’ check box:

Save the project. Your XDC file should be updated with Vivado ILA constraints as shown below:

Implement and Generate the PDI image.

TSM Program Trigger

The following TSM program triggers after the LTSSM goes to L0 twice i.e. the LTSSM trains to L0, comes off L0 and then goes back to L0.

The waveform screenshot below shows the capture after the above TSM program has triggered.

If you want to check if the LTSSM goes to L0 a specific number of times, you could program your TSM as follows. The code below triggers after the LTSSM goes to L0 5 times.

Note: TSM programs should be compiled without error before setting the trigger. Click on the highlighted icon below to compile your code.

The screenshot below shows that the ILA is triggered after the LTSSM goes to L0 for the fifth time. This indicates an unstable link. To verify the counter value, you can check the status window as shown below. The screenshot shows the Counter0 value as ‘5’ when the ILA triggers.

The screenshot below shows that the LTSSM ends in ‘0C’ in the given window capture. You can use a TSM program to trigger when the LTSSM comes off ‘0C’.

The TSM program below waits for the LTSSM to go to 0C in state0. Once the LTSSM goes to 0C, the state machine moves to state1 and waits there until the LTSSM comes off 0C. As soon as the LTSSM value becomes different than 0C, it triggers. The waveform below shows that the LTSSM goes to 0B from 0C.

LTSSM is one of the key signals to focus on when debugging PCIe issues. During a PCIe debug, it would be helpful to track the LTSSM sequence it should follow in a successful link training as defined by the specification. This is possible in Vivado ILA with the Advanced Debug Trigger feature by writing a TSM program. The example code below tracks whether the LTSSM goes from 0B to 0D and then to 0C.

During a Gen3 link training process, the LTSSM goes through the various equalization phases. You can check whether the equalization phase sequence has been followed or not by writing a TSM program as shown below.

The examples provided above are just some of the scenarios in which the Advanced Trigger feature in Vivado ILA can be used for debugging PCIe issues. Some other triggering scenarios are listed below.

1. Check which LTSSM state the equalization phase (phase – 0,1,2,3) falls back to during an unsuccessful Gen3 link training process.
2. Trigger on a specific packet arriving at the user logic interface.
3. If you are sending 10 Memory Read packets to the endpoint, check whether the user logic sends back 10 completions or not.
4. If the descrambler module is enabled, you can check if more than a specific number of TLPs are being received or sent on the PIPE interface.

With the TSM programming feature, Vivado ILA provides a powerful tool to debug PCIe issues by allowing you to set triggers for complex trigger conditions.

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Source: https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Using-the-ILA-Advanced-Trigger-Feature-to-debug-designs-with-the/ba-p/1260220