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Tag: logic-in-memory

Scalable CMOS back-end-of-line-compatible AlScN/two-dimensional channel ferroelectric field-effect transistors – Nature Nanotechnology

Migliato Marega, G. et al. Logic-in-memory based on an atomically thin semiconductor. Nature 587, 72–77 (2020).Article  CAS  Google Scholar  Wang, Z. et al....

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Phase-controllable large-area two-dimensional In2Se3 and ferroelectric heterophase junction

Si, M. et al. A ferroelectric semiconductor field-effect transistor. Nat. Electron. 2, 580–586 (2019).Article  CAS  Google Scholar  Wu, J. B. et al. High...

Framework Based on an RISC-V Microprocessor Supporting LiM Operations

A new technical paper titled “RISC-Vlim, a RISC-V Framework for Logic-in-Memory Architectures” was published by researchers at Politecnico di Torino (Italy), Univerity of Tor...

NAND and NOR logic-in-memory comprising silicon nanowire feedback field-effect transistors

Demonstrates that the NAND and NOR LIM has promising potential to resolve power and processing speed issues. NAND and NOR LIM composed of silicon nanowire (SiNW) feedback field-effect transistors (FBFETs) to verify universal gate functions, where the configuration of the SiNW FBFETs maintains conventional CMOS logic gates

The post NAND and NOR logic-in-memory comprising silicon nanowire feedback field-effect transistors appeared first on Semiconductor Engineering.

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