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Tag: CXL

Ethernet advances will end InfiniBand’s lead in AI nets

Three imminent improvements to the Ethernet standard will make it a better alternative to host AI workloads, and that will see vendors back the...

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Blog Review: Jan. 10

Systems & Design ...

HPC News Bytes 20240108: Ericsson and the Intel 4 Process, AI and VC in 2023, Samsung and CXL for RHEL, Quantum Cybersecurity – High-Performance...

A good January morning to you! Here’s a brief (5:14) run-down of the latest goings on in HPC-AI:– Ericsson may beat Intel to the...

Alphawave Semiconductor Powering Progress – Semiwiki

Do you know who had another great year? Alphawave Semi did. Despite being relatively young in the industry (founded in 2017), the company has...

SK hynix unveils ultra-high performance memory tech at CES 2024 | IoT Now News & Reports

SK hynix Inc. will be presenting its technology for ultra-high performance memory products at CES 2024. These memory products are expected to play a...

Startup Funding: September 2023

Chip-to-chip and data center I/O drew investor interest in September, including support for several startups developing Compute Express Link (CXL) solutions. Elsewhere in the...

Chip Industry Week In Review

By Liz Allan, Jesse Allen, and Karen Heyman Global semiconductor equipment billings dipped 2% year-over-year to US$25.8 billion in Q2, and slipped 4% compared with...

Sweeping Changes For Leading-Edge Chip Architectures

Chipmakers are utilizing both evolutionary and revolutionary technologies to achieve orders of magnitude improvements in performance at the same or lower power, signaling a...

The Ultimate SaaS Pricing Resources Guide – OpenView

Pricing is a SaaS company’s most efficient profit lever, but it’s also one of the easiest things to screw up. Nailing your SaaS pricing...

Processor Tradeoffs For AI Workloads

AI is forcing fundamental shifts in chips used in data centers and in the tools used to design them, but it also is creating...

DRAM Translation Layer, Mechanism for Flexible Address Mapping and Data Migration Within CXL-Based Memory Devices

A technical paper titled “DRAM Translation Layer: Software-Transparent DRAM Power Savings for Disaggregated Memory” was published by researchers at Seoul National University. Abstract: “Memory disaggregation is...

Chiplet Interconnect Challenges and Standards – Semiwiki

For decades now I’ve watched the incredible growth of SoCs in terms of die size, transistor count, frequency and complexity. Instead of placing all...

Server Design With Pin-Efficient CXL Interface (Georgia Tech)

A new technical paper titled “A Case for CXL-Centric Server Processors” was written by researchers at Georgia Tech. Abstract:“The memory system is a major performance...

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