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Launching an R5 standalone application from the Vitis GUI on Versal running Linux

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PetaLinux project

This PetaLinux project for this demo is built using a VCK190 BSP.

  1. Create the PetaLinux project using the VCK190 BSP.

    $ petalinux-create -t project -n vck190_bsp -s xilinx-vck190-es1-v2020.2-final.bsp
  2. Configure the project. 

    $ cd vck190_bsp/
    $ petalinux-config
  3. Because we will be using Vitis to launch/debug the R5 application ELF using JTAG on the target and Linux is already running on the target, we will encounter the CPU idle issue as described in (Xilinx Answer 69143).
    You can use any of the work-around methods described in the Answer Record to resolve this issue.
    I have used Method 3 and disabled cpu-idle in bootargs:
    $ vim project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi
    /include/ "system-conf.dtsi"
    / { chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused cpuidle.off=1 root=/dev/ram0 rw"; stdout-path = "serial0:115200"; };
    }; &amba { zyxclmm_drm { compatible = "xlnx,zocl-versal"; };
    };​
  4. Build the project

    $ petalinux-build
  5. Package the BOOT.bin
    $ petalinux-package --boot --plm --psmfw --u-boot --dtb --force​

Vitis project

  • Create a standalone Hello World application targeting the R5 processor. Click browse and import your custom XSA or you can select the vck190.xsa from fixed platforms.
  • Select R5-0 as the target processor for the application project. 

target-r5-select.png

  • Select the domain for the application project. In this example we will be using the Standalone domain.

domain-select.png

  • Select the Hello World template for the application and click on Finish.
  • In your lscript.ld, place the .vectors section in TCM and all other sections in DDR.
    See the attached lscript.txt (Rename to lscript.ld before using).

Note: if using the XSA from a Petalinux 2020.2 bsp, lscript.ld uses ai_engine_0_AIE_ARRAY_0 as memory to map the different sections.

Please change this to use DDR instead.

  • Build the Vitis project (Ctrl + B).
  • Set up the Debug Configuration. 

debug-config.png

  • Select Standalone Application Debug using the TCF agent.
    Set the connection as Local if you are connected to the board locally, or else click on New and set up the New Target connection by providing the hw_server URL address.
    Test the connection to make sure that your host machine is able to talk to the board. 

tcf-setup.png

  • In the Application tab, uncheck Reset processor

application-tab.png

  • Uncheck Reset entire system and Program Device in the Target Setup tab

target-setup.png

Testing on hardware

  1. Boot the Linux images generated on to your board. For SD boot mode, copy the BOOT.bin, image.ub and boot.scr to the SD card.
    Switch the boot mode pins to SD and power up the board.
  2. Power up the R5 cores and set up the TCM memories. A complete command list can be found in the user guide here.
    1. Set RPU-0 in split mode.

      root@xilinx-vck190-es1-2020_2:~# echo pm_ioctl 0x18110005 1 1 0 > /sys/kernel/debug/zynqmp-firmware/pm
    2. Request TCM0-A and TCM0-B.
      root@xilinx-vck190-es1-2020_2:~# echo pm_request_node 0x1831800b > /sys/kernel/debug/zynqmp-firmware/pm root@xilinx-vck190-es1-2020_2:~# echo pm_request_node 0x1831800c > /sys/kernel/debug/zynqmp-firmware/pm
    3. Wake up RPU-0.
      root@xilinx-vck190-es1-2020_2:~# echo pm_request_wakeup 0x18110005 1 0 0 > /sys/kernel/debug/zynqmp-firmware/pm
      
  3. In Vitis, launch your application in Debug mode.
    It will halt at the first line of your main function. Use F6 to step-over through the code. 

single-step.png

Observe the print-out on the UART console.

plnx-console.png

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Source: https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Launching-an-R5-standalone-application-from-the-Vitis-GUI-on/ba-p/1225679

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