Introduction 

This tutorial will cover the steps to port the DisplayPort 1.4 RX Subsystem Example design from the ZCU102 Board to the ZCU106 Board in the 2021.1 release. 

For any issues please refer to the DisplayPort 1.4 RX Subsystem and DisplayPort 1.4 TX Subsystem Product Guides and review the Example design instructions provided in each. 

ZCU102 DisplayPort 1.4 RX Example design Overview

The DisplayPort 1.4 RX Subsystem Example design is intended to display the properties of the DisplayPort 1.4 RX Subsystem and other similar IP. 

The ZCU102 Example design requires the use of the ZCU102 Board, and the Tokyo Electron Device Limited (TED) TB-FMCH-VFMC-DP module.

There are several different example design options available. 

For a ZCU102 board we are only looking at the GTHE4 options:

• RX Only
• TX Only
• FB Pass-through without HDCP1.3/HDCP2.2/2.3
• FB Pass-through with HDCP1.3 and HDCP2.2/2.3
• MST FB Pass-through without HDCP1.3 and TX only

We will be using these same options when porting the design to the ZCU106 Board.

The following steps can be used to port the ZCU102 example design to the ZCU106 board.

For this example I used the FB Pass-through without HDCP1.3/HDCP2.2/2.3 design, but any of the designs can be used with this process.

Note: these steps are for instruction purposes, and there is more than one way to port a design.

• Open a new Vivado project with the ZCU102 board selected as the target.

• Select “Create Block Design”
• Add a “Video DisplayPort 1.4 RX Subsystem” IP block
• Double click and select the proper Example design selection

• Apply changes and close the editing window
• Right Click and select “Open IP Example Design”
• Wait for the project to fully open and load.
• Go to Project Manager->Project Summary->Project Part

• Go to Device and change it to ZCU106, then click Apply and OK.

• Wait for it to load then select “Open Block Design”
• Select “Report IP Status” in the yellow popup at the top of the page

• Ensure that all IP are selected and click “Upgrade Selected”

• If prompted, do not click “Regenerate Output Products”.
• Double click on the Video PHY Controller block and change the GT: Starting Channel Location to X0Y12 (the GT location is found from the ZVU106 schematic)
• Validate the Block Design
• Run Synthesis
• Open the Synthesized design
• Under I/O ports change all of the “Package Pin” values to the new values listed below. (You can also refer to the attached excel spreadsheet)

• Any of the Red “I/O Std” clock sources change to LVCMOS18 

• Save the project
• Run Synthesis and Implementation
• Generate Bitstream
• Export Hardware and Include Bitstream
• Launch Vitis
• Create a Platform Project
• Select the exported XSA file
• Build the Project
• Select the Import Examples under the dp14rxss driver in the BSP under the Standalone on psu_cortex53_0
• Select the appropriate example project
• Build the project
• Debug on the ZCU106 board with the appropriate hardware connections, and select play when ready 
• You should be done! 

(Note: you might need to use the ZCU106 SCUI and set the FMC VADJ to 1.8V)

For any questions or concerns please refer to the Video and Audio Forum.