Introduction

This blog entry will cover important information you should understand before designing with Memory Interfaces on Versal™ ACAP devices. 

 It will additionally link you to relevant documentation, tutorials, and example designs.

You can find all of our Versal related blogs here.

IP Offerings

Versal ACAP offers the hardened Integrated DDR Memory Controller (DDRMC) along with soft memory interface IP options.

Additionally, the Performance AXI Traffic Generator is available to stimulate the Memory IP in both simulation and post-synthesis for hardware analysis.

The Versal Integrated DDRMC is the preferred solution due to its power, resource utilization, and timing closure savings.

The DDRMC has programmable network on chip (NoC) interface ports and is designed to handle multiple streams of traffic.

Additionally, it supports Quality of Service (QoS) classes to ensure appropriate prioritization of commands.

The NoC is a configurable AXI network used for sharing data between IP endpoints in the programmable logic (PL), the processing system (PS), and other hard blocks. This device-wide infrastructure is a high-speed, integrated data path with dedicated switching.

The Versal soft IP offerings are located within the PL and are similar to the soft memory interface IP offerings in the UltraScale/UltraScale+ device families.

Table 1: Versal IP Offerings

Design Flows

There are two main design tools when targeting Versal ACAPs:

• Vivado® Tools Design Flow to accelerate high-level FPGA design and verification
• Vitis™ Environment Design Flow to build accelerated applications

For NoC and DDRMC designs, Vivado IP Integrator (IPI) is required. For the above listed soft IP, both RTL instantiation and IPI are supported.

For assistance using IP Integrator, visit the Vivado – Using IP Integrator Design Hub.

For design flow best practices and detailed memory interface IP walk-throughs, visit the Versal ACAP Design Guide (UG1273 Chapter 4 – “Design Flow”) and the above listed IP Product Guides.

The Example Designs referenced below are also available and provide excellent examples to help get started.

All Versal ACAP designs require the CIPS IP as it contains the PMC used to boot the device. For more information, see the Control Interface and Processing System IP Product Guide (PG352).

Getting Started with NoC/DDRMC

Designing with NoC and DDRMC is new to Versal ACAP and different from previous Xilinx device families.

To help you get started:

• Follow Pin and PCB Requirements: Ensure that your DDRMC Pin-out and PCB adhere to all requirements.
  Utilize the “Obtaining and Verifying Versal ACAP Memory Pinouts” tutorial on GitHub and strictly follow requirements in UG863, then be sure to simulate your memory interfaces at the PCB level.

  Coming Soon, you will be able to follow “Versal DDR4 and LPDDR4 Timing Models for Hyperlynx DDRx Wizard: A Tutorial for Signal Integrity Simulations“.
  This blog will be updated once it is available.

Design Process Hubs

Xilinx documentation is organized around a set of user design processes to help you find relevant content for your design needs.
Visit these Design Process Hubs for complete information related to your design process:

Example Designs and Tutorials

Additional Resources

Source: https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Getting-Started-with-Versal-Memory-Interfaces/ba-p/1192335