Connect with us

Semiconductor

DuPont Microcircuit Materials Introduces New Sinter Silver Product

Avatar

Published

on

News Image

“This newest offering demonstrates a range of superior technical properties to meet different customers’ manufacturing process requirements. We are excited about introducing this new product to our customers globally and expect very positive results from early adoption customers.”

DuPont (NYSE:DD) today introduced an advanced screen printable sinter silver product for power semiconductor die attach that improves reliability and productivity in the power module assembly process.

The product, DuPont™ DA510, is an advanced pressure sintering silver paste that delivers high thermal and electrical conductivity, fast takt time and superior sintered density. The associated thermal cycle reliability enables the assembly of high performance and high-density power modules for the automotive power electronics industry segment. The new sintering silver, from the DuPont Microcircuit Materials business, is ideally suited to enable the utilization of wide band semiconductor MOSFET chips in the rapidly increasing auto electrification market and beyond. DuPont™ DA510 has also shown promising results for potential use in power module heat sink attachment applications due to its ability for high quality, large area prints.

“The DuPont™ DA510 sinter silver offers excellent reliability and productivity and we will continue to innovate and build on this technology,” said Peter Weigand, Global Automotive Segment Manager, DuPont Microcircuit Materials. “This newest offering demonstrates a range of superior technical properties to meet different customers’ manufacturing process requirements. We are excited about introducing this new product to our customers globally and expect very positive results from early adoption customers.”

Weigand noted that DuPont continues to invest in research, development and intellectual property involving die attach paste technology to address customer needs in this growing market segment.

DuPont Microcircuit Materials has over 50 years of experience in the development, manufacture, sale and support of specialized thick film compositions for a wide variety of electronic applications in the display, automotive, biomedical, industrial, military and telecommunications markets.

For more information on DuPont Microcircuit Materials, please visit http://mcm.dupont.com.

About DuPont

DuPont (NYSE: DD) is a global innovation leader with technology-based materials and solutions that help transform industries and everyday life. Our employees apply diverse science and expertise to help customers advance their best ideas and deliver essential innovations in key markets including electronics, transportation, construction, water, healthcare and worker safety. More information about the company, its businesses and solutions can be found at http://www.dupont.com. Investors can access information included on the Investor Relations section of the website at investors.dupont.com.

# # #

DuPont™, the DuPont Oval Logo, and all trademarks and service marks denoted with ™, SM or ® are owned by affiliates of DuPont de Nemours, Inc. unless otherwise noted.

3/12/21

For further information contact:

Ted Sikorski

609-280-0068

ted.sikorski@dupont.com

Share article on social media or email:

Coinsmart. Beste Bitcoin-Börse in Europa
Source: https://www.prweb.com/releases/dupont_microcircuit_materials_introduces_new_sinter_silver_product/prweb17794124.htm

Semiconductor

Launching an R5 standalone application from the Vitis GUI on Versal running Linux

Avatar

Published

on

PetaLinux project

This PetaLinux project for this demo is built using a VCK190 BSP.

  1. Create the PetaLinux project using the VCK190 BSP.

    $ petalinux-create -t project -n vck190_bsp -s xilinx-vck190-es1-v2020.2-final.bsp
  2. Configure the project. 

    $ cd vck190_bsp/
    $ petalinux-config
  3. Because we will be using Vitis to launch/debug the R5 application ELF using JTAG on the target and Linux is already running on the target, we will encounter the CPU idle issue as described in (Xilinx Answer 69143).
    You can use any of the work-around methods described in the Answer Record to resolve this issue.
    I have used Method 3 and disabled cpu-idle in bootargs:
    $ vim project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi
    /include/ "system-conf.dtsi"
    / { chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused cpuidle.off=1 root=/dev/ram0 rw"; stdout-path = "serial0:115200"; };
    }; &amba { zyxclmm_drm { compatible = "xlnx,zocl-versal"; };
    };​
  4. Build the project

    $ petalinux-build
  5. Package the BOOT.bin
    $ petalinux-package --boot --plm --psmfw --u-boot --dtb --force​

Vitis project

  • Create a standalone Hello World application targeting the R5 processor. Click browse and import your custom XSA or you can select the vck190.xsa from fixed platforms.
  • Select R5-0 as the target processor for the application project. 

target-r5-select.png

  • Select the domain for the application project. In this example we will be using the Standalone domain.

domain-select.png

  • Select the Hello World template for the application and click on Finish.
  • In your lscript.ld, place the .vectors section in TCM and all other sections in DDR.
    See the attached lscript.txt (Rename to lscript.ld before using).

Note: if using the XSA from a Petalinux 2020.2 bsp, lscript.ld uses ai_engine_0_AIE_ARRAY_0 as memory to map the different sections.

Please change this to use DDR instead.

  • Build the Vitis project (Ctrl + B).
  • Set up the Debug Configuration. 

debug-config.png

  • Select Standalone Application Debug using the TCF agent.
    Set the connection as Local if you are connected to the board locally, or else click on New and set up the New Target connection by providing the hw_server URL address.
    Test the connection to make sure that your host machine is able to talk to the board. 

tcf-setup.png

  • In the Application tab, uncheck Reset processor

application-tab.png

  • Uncheck Reset entire system and Program Device in the Target Setup tab

target-setup.png

Testing on hardware

  1. Boot the Linux images generated on to your board. For SD boot mode, copy the BOOT.bin, image.ub and boot.scr to the SD card.
    Switch the boot mode pins to SD and power up the board.
  2. Power up the R5 cores and set up the TCM memories. A complete command list can be found in the user guide here.
    1. Set RPU-0 in split mode.

      root@xilinx-vck190-es1-2020_2:~# echo pm_ioctl 0x18110005 1 1 0 > /sys/kernel/debug/zynqmp-firmware/pm
    2. Request TCM0-A and TCM0-B.
      root@xilinx-vck190-es1-2020_2:~# echo pm_request_node 0x1831800b > /sys/kernel/debug/zynqmp-firmware/pm root@xilinx-vck190-es1-2020_2:~# echo pm_request_node 0x1831800c > /sys/kernel/debug/zynqmp-firmware/pm
    3. Wake up RPU-0.
      root@xilinx-vck190-es1-2020_2:~# echo pm_request_wakeup 0x18110005 1 0 0 > /sys/kernel/debug/zynqmp-firmware/pm
      
  3. In Vitis, launch your application in Debug mode.
    It will halt at the first line of your main function. Use F6 to step-over through the code. 

single-step.png

Observe the print-out on the UART console.

plnx-console.png

Coinsmart. Beste Bitcoin-Börse in Europa
Source: https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Launching-an-R5-standalone-application-from-the-Vitis-GUI-on/ba-p/1225679

Continue Reading

Semiconductor

Launching an R5 standalone application from the Vitis GUI on Versal running Linux

Avatar

Published

on

PetaLinux project

This PetaLinux project for this demo is built using a VCK190 BSP.

  1. Create the PetaLinux project using the VCK190 BSP.

    $ petalinux-create -t project -n vck190_bsp -s xilinx-vck190-es1-v2020.2-final.bsp
  2. Configure the project. 

    $ cd vck190_bsp/
    $ petalinux-config
  3. Because we will be using Vitis to launch/debug the R5 application ELF using JTAG on the target and Linux is already running on the target, we will encounter the CPU idle issue as described in (Xilinx Answer 69143).
    You can use any of the work-around methods described in the Answer Record to resolve this issue.
    I have used Method 3 and disabled cpu-idle in bootargs:
    $ vim project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi
    /include/ "system-conf.dtsi"
    / { chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused cpuidle.off=1 root=/dev/ram0 rw"; stdout-path = "serial0:115200"; };
    }; &amba { zyxclmm_drm { compatible = "xlnx,zocl-versal"; };
    };​
  4. Build the project

    $ petalinux-build
  5. Package the BOOT.bin
    $ petalinux-package --boot --plm --psmfw --u-boot --dtb --force​

Vitis project

  • Create a standalone Hello World application targeting the R5 processor. Click browse and import your custom XSA or you can select the vck190.xsa from fixed platforms.
  • Select R5-0 as the target processor for the application project. 

target-r5-select.png

  • Select the domain for the application project. In this example we will be using the Standalone domain.

domain-select.png

  • Select the Hello World template for the application and click on Finish.
  • In your lscript.ld, place the .vectors section in TCM and all other sections in DDR.
    See the attached lscript.txt (Rename to lscript.ld before using).

Note: if using the XSA from a Petalinux 2020.2 bsp, lscript.ld uses ai_engine_0_AIE_ARRAY_0 as memory to map the different sections.

Please change this to use DDR instead.

  • Build the Vitis project (Ctrl + B).
  • Set up the Debug Configuration. 

debug-config.png

  • Select Standalone Application Debug using the TCF agent.
    Set the connection as Local if you are connected to the board locally, or else click on New and set up the New Target connection by providing the hw_server URL address.
    Test the connection to make sure that your host machine is able to talk to the board. 

tcf-setup.png

  • In the Application tab, uncheck Reset processor

application-tab.png

  • Uncheck Reset entire system and Program Device in the Target Setup tab

target-setup.png

Testing on hardware

  1. Boot the Linux images generated on to your board. For SD boot mode, copy the BOOT.bin, image.ub and boot.scr to the SD card.
    Switch the boot mode pins to SD and power up the board.
  2. Power up the R5 cores and set up the TCM memories. A complete command list can be found in the user guide here.
    1. Set RPU-0 in split mode.

      root@xilinx-vck190-es1-2020_2:~# echo pm_ioctl 0x18110005 1 1 0 > /sys/kernel/debug/zynqmp-firmware/pm
    2. Request TCM0-A and TCM0-B.
      root@xilinx-vck190-es1-2020_2:~# echo pm_request_node 0x1831800b > /sys/kernel/debug/zynqmp-firmware/pm root@xilinx-vck190-es1-2020_2:~# echo pm_request_node 0x1831800c > /sys/kernel/debug/zynqmp-firmware/pm
    3. Wake up RPU-0.
      root@xilinx-vck190-es1-2020_2:~# echo pm_request_wakeup 0x18110005 1 0 0 > /sys/kernel/debug/zynqmp-firmware/pm
      
  3. In Vitis, launch your application in Debug mode.
    It will halt at the first line of your main function. Use F6 to step-over through the code. 

single-step.png

Observe the print-out on the UART console.

plnx-console.png

Coinsmart. Beste Bitcoin-Börse in Europa
Source: https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Launching-an-R5-standalone-application-from-the-Vitis-GUI-on/ba-p/1225679

Continue Reading

Semiconductor

Launching an R5 standalone application from the Vitis GUI on Versal running Linux

Avatar

Published

on

PetaLinux project

This PetaLinux project for this demo is built using a VCK190 BSP.

  1. Create the PetaLinux project using the VCK190 BSP.

    $ petalinux-create -t project -n vck190_bsp -s xilinx-vck190-es1-v2020.2-final.bsp
  2. Configure the project. 

    $ cd vck190_bsp/
    $ petalinux-config
  3. Because we will be using Vitis to launch/debug the R5 application ELF using JTAG on the target and Linux is already running on the target, we will encounter the CPU idle issue as described in (Xilinx Answer 69143).
    You can use any of the work-around methods described in the Answer Record to resolve this issue.
    I have used Method 3 and disabled cpu-idle in bootargs:
    $ vim project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi
    /include/ "system-conf.dtsi"
    / { chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused cpuidle.off=1 root=/dev/ram0 rw"; stdout-path = "serial0:115200"; };
    }; &amba { zyxclmm_drm { compatible = "xlnx,zocl-versal"; };
    };​
  4. Build the project

    $ petalinux-build
  5. Package the BOOT.bin
    $ petalinux-package --boot --plm --psmfw --u-boot --dtb --force​

Vitis project

  • Create a standalone Hello World application targeting the R5 processor. Click browse and import your custom XSA or you can select the vck190.xsa from fixed platforms.
  • Select R5-0 as the target processor for the application project. 

target-r5-select.png

  • Select the domain for the application project. In this example we will be using the Standalone domain.

domain-select.png

  • Select the Hello World template for the application and click on Finish.
  • In your lscript.ld, place the .vectors section in TCM and all other sections in DDR.
    See the attached lscript.txt (Rename to lscript.ld before using).

Note: if using the XSA from a Petalinux 2020.2 bsp, lscript.ld uses ai_engine_0_AIE_ARRAY_0 as memory to map the different sections.

Please change this to use DDR instead.

  • Build the Vitis project (Ctrl + B).
  • Set up the Debug Configuration. 

debug-config.png

  • Select Standalone Application Debug using the TCF agent.
    Set the connection as Local if you are connected to the board locally, or else click on New and set up the New Target connection by providing the hw_server URL address.
    Test the connection to make sure that your host machine is able to talk to the board. 

tcf-setup.png

  • In the Application tab, uncheck Reset processor

application-tab.png

  • Uncheck Reset entire system and Program Device in the Target Setup tab

target-setup.png

Testing on hardware

  1. Boot the Linux images generated on to your board. For SD boot mode, copy the BOOT.bin, image.ub and boot.scr to the SD card.
    Switch the boot mode pins to SD and power up the board.
  2. Power up the R5 cores and set up the TCM memories. A complete command list can be found in the user guide here.
    1. Set RPU-0 in split mode.

      root@xilinx-vck190-es1-2020_2:~# echo pm_ioctl 0x18110005 1 1 0 > /sys/kernel/debug/zynqmp-firmware/pm
    2. Request TCM0-A and TCM0-B.
      root@xilinx-vck190-es1-2020_2:~# echo pm_request_node 0x1831800b > /sys/kernel/debug/zynqmp-firmware/pm root@xilinx-vck190-es1-2020_2:~# echo pm_request_node 0x1831800c > /sys/kernel/debug/zynqmp-firmware/pm
    3. Wake up RPU-0.
      root@xilinx-vck190-es1-2020_2:~# echo pm_request_wakeup 0x18110005 1 0 0 > /sys/kernel/debug/zynqmp-firmware/pm
      
  3. In Vitis, launch your application in Debug mode.
    It will halt at the first line of your main function. Use F6 to step-over through the code. 

single-step.png

Observe the print-out on the UART console.

plnx-console.png

Coinsmart. Beste Bitcoin-Börse in Europa
Source: https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Launching-an-R5-standalone-application-from-the-Vitis-GUI-on/ba-p/1225679

Continue Reading

Semiconductor

Ferroelectric, hafnium oxide based transistors for digital beyond von-Neumann computing

Avatar

Published

on

Home

TECHNICAL PAPERS

HfO2-based FeFETs: challenges & mitigation strategies

popularity

Source: AIP Applied Physics Letters, published 2/4/2021.

 Evelyn T. Breyer1,  Halid Mulaosmanovic1,  Thomas Mikolajick1,2, and  Stefan Slesazeck1

  • 1Nanoelectronic Materials Laboratory (NaMLab) gGmbH, 01187 Dresden, Germany
  • 2Chair of Nanoelectronics, TU Dresden, 01187 Dresden, Germany

Technical paper link is here

Coinsmart. Beste Bitcoin-Börse in Europa
Source: https://semiengineering.com/ferroelectric-hafnium-oxide-based-transistors-for-digital-beyond-von-neumann-computing/

Continue Reading
Esports5 days ago

Dota 2 patch 7.29b brings nerfs to Phantom Lancer and Lifestealer amongst other hero balance changes

Esports5 days ago

Apex Legends Season 9 will add new hero, fix Banglore bugs

Esports5 days ago

Code S: Trap & Zest advance to RO8, playoff bracket set

Esports5 days ago

New CSGO Update Makes Items Purchased From Store Non Tradable for a Week

Blockchain3 days ago

Mining Bitcoin: How to Mine Bitcoin

Esports5 days ago

Radiant Valorant streamer Solista banned for cheating on live stream

Esports5 days ago

How to Calculate Steam Market Tax on CSGO Items

Fintech4 days ago

Fintech offers brokers better commissions after BID

Esports4 days ago

OWL 2021 Power Rankings – #9 Guangzhou Charge

Blockchain4 days ago

Stanislovas Tomas im Interview: „NFTs können unsere Gesellschaft verändern“

Esports5 days ago

OWL 2021 Power Rankings – #10 Washington Justice

Esports4 days ago

xQc Banned From NoPixel GTA RP Server Once Again

PR Newswire3 days ago

Hello Pal Signs Definitive Purchase Agreement to Acquire Interest in Dogecoin/Litecoin Mining Assets

Esports4 days ago

CDL Challengers Elite Stage 3 Preview

Coinbase hourly chart
Blockchain3 days ago

Coinbase Addresses Future Revenue Concerns With Plans to Become Crypto’s Amazon

Esports5 days ago

Zayt Retires From Competitive Fortnite For The Second Time

Esports4 days ago

Twitch streamer Lando Norris takes Italian F1 Grand Prix podium

Esports5 days ago

Dota 2: DPC Weekly Recap — SEA Apr 12-17, 2021

Esports4 days ago

Three takeaways from the SWT Japan Ultimate Online Qualifier

Esports4 days ago

Cloud9 Perkz says Kassadin can’t ever be balanced in LoL

Trending