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Diagnosing MPSoC PS DDR Using The zynqmp_dram_test Application

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Introduction:

In this blog entry we will discover how to run diagnostic tests on MPSoC PS DDR using our zynqmp_dram_test application on Zynq UltraScale+ MPSoC. In this example we will be using Vivado 2020.2 and Vitis™ 2020.2.

We will see:

  • How to create a simple design with PS DDR in Vivado.
  • How to generate an XSA file.
  • How to create a Vitis application project using the zynqmp_dram_test template.
  • How to run the zynqmp_dram_test application on Zynq UltraScale+ MPSoC.
  • How to pull the latest version of the zynqmp_dram_test application from GitHub.

Requirements:

  • Vivado 2020.2
  • Vitis 2020.2
  • Zynq UltraScale+ MPSoC target

ZynqMP DRAM Diagnostics Test:

The Zynq MP DRAM diagnostics test is a stand-alone program running on a single Zynq MPSoC Cortex-A53 processor, executing out of OCM. The program uses the UART for interactive operations. A small menu is displayed, and the user can choose to run various memory tests.

The test offers many memory tests with configurable data patterns and configurable memory ranges. It also offers Read and Write Eye Measurements.

Important: Do not run this application from DDR as the code will be overwritten by the write accesses done by the application itself to DDR.


Steps:

Open Vivado.

Create a new project:

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Set the project name. For this example we will set it to  ”zynq_mp_dram_diagnostic”:

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Click Next.

Select “RTL Project”:

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Select a Zynq UltraScale+ part from the Parts tab.

Click Next, then Finish.

Now we need to create a Block Design, in which we will create our design.

Click on “Create Block Design”:

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Select the Block Design name. In this example we just used the default one:

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After creating the Block Design, click “Add IP” in the Diagram window:

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Search for MPSoC IP, then double click on “Zynq UltraScale+ MPSoC” to instantiate it:

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Double click on the MPSoC IP to configure our MPSoC.

From the I/O Configuration tab, enable the UART0 peripheral. We need this to get the test output.

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From the Clock Configuration tab, set the GPU clock to VPLL and the DDR clock to DPLL:

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From the DDR Configuration, set the DDR configuration that matches the DDR setup on your target:

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Connect the clocks as follows:

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The design is now ready, but there are some extra steps required so that we can export the hardware, create the XSA file and use it with Vitis to create the Zynq DRAM Diagnostics test.

Right click on the Block Design, then “Create HDL Wrapper”:

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Right click on the Block Design, then “Generate Output Products”:

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Click “Generate”:

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You will get this pop up window once the Output Products is generated:

abouassi_16-1615404918054.png

After generating the Output Products, we need to create the XSA file.

– From the Main menu select File > Export > Export Hardware.

abouassi_17-1615404918059.png

Click Next:

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Set the “Pre-synthesis” option. Because we do not have anything on the PL, there is no need to generate the Bitstream and to include it in our XSA file:

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Set the name and the location for the XSA file:

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Click Finish:

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Now, the XSA file has been created and we need to open Vitis to create an application project using that XSA file.

You can open Vitis from Vivado.

From the Main menu select Tools > Launch Vitis IDE:

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Select the Vitis workspace directory:

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To Create an Application Project click on File > Application Project:

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Click Next:

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Select the “Create a new platform from hardware (XSA)” tab:

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Click the “Browse” button and select the XSA file that we have created previously. Make sure to check the “Generate boot components” check-box, so that the FSBL will be created automatically. The FSBL is needed to boot the board before loading the application:

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Set the Application project name and select the processor in which you want to run the application:

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Create a  standalone domain for our DDR application test:

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Then select the “Zynq MP DRAM Tests” template:

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This will pull the Zynq MP DRAM test from your Xilinx tool installation directory. If you are using an old tool version and you want to use the latest version of this application, see the “Pull Zynq MP DRAM from GitHub” section below.

To build the application, first select it then click on the build icon:

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This will compile the application and create zynqmp_dram_diagnostic.elf

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Before running the application, the boot mode should be set to JTAG boot mode on the target, then connect it to your host.

Use any Serial Terminal utility to connect to the board UART port.

To run the application, right click on the application project and select Run As > Run Configurations:

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Double click on “Single Application Debug” to create a new debug/run configuration:

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Click on the newly created configuration, then check the configuration:

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On the “Application” tab, uncheck the “Stop at ‘main’” option, as we do not need to stop at main when running our application:

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On the “Target Setup” tab, make sure to use the FSBL flow for initialization, then click Run:

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On your terminal, you will see that the application has started executing and you will get the following output:

abouassi_39-1615404918190.png

To ensure correct function of the test, you should check that DDR calibration has been done successfully. This can be done by checking the PHY General Status Register 0 (PGSR0) at 0xFD080030.

To get the best out of the test, it is always good to do the following:

  • Perform the read eye analysis test using the option ‘r’ and check the resulting width and center of the eye.
  • Perform the write eye analysis test using the option ‘w’ and check the resulting width and center of the eye.
  • Loop the Memory Test with a high number of iterations via the ‘Select Number of Iterations….’ Using the option ‘l’, to try and replicate data errors.
  • Target the entire available memory range using the option 0-9 that matches your memory setup size or use ‘m’ or ‘g’ for any other sizes.
  • Enable Verbose Mode for better error reporting using the option ‘v’.
  • Enable Data Cache using the option ‘o’.
  • DDR configurations with ECC enabled have the data cache disabled, which reduces bandwidth and stress on the interface. It is recommended to disable ECC for higher memory stress tests.

For details on how to use the ZynqMP DRAM tests you can hit ‘h’ to print help, or you can open the test document “ZYNQMP_DRAM_DIGNOSTICS_TEST.docx” for further details:

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Pull Zynq MP DRAM from GitHub:

The latest version of the ZynqMP DRAM test can be found on GitHub at the following location:

https://github.com/Xilinx/embeddedsw/tree/master/lib/sw_apps/zynqmp_dram_test

After downloading the zynqmp_dram_test folder, create a new folder in a location of your choice. In this example we name it “repo”. Create another folder within it and name it sw_app.

Then copy the zynqmp_dram_test there. You will end up with a similar folder hierarchy to the example below:

abouassi_41-1615404918193.png

You will need to add this folder as a repo to Vitis before creating our application project.

– From the Main menu open Xilinx  > Repositories:

abouassi_42-1615404918199.png

Click New and then choose the path of the repo folder we have created:

abouassi_43-1615404918206.png

Click on “Apply” then “Apply and Close”.

Now, when you create a new application project using the zynq_mp_dram_test, it will be fetched from the repo folder rather than from your installation directory.

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Source: https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Diagnosing-MPSoC-PS-DDR-Using-The-zynqmp-dram-test-Application/ba-p/1216727

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